Semiconductor Manufacturing: A Practical Reference

A polished prime wafer is a single-crystal silicon disc, grown and sliced as described in manufacturing-processes 014, then lapped, edge-profiled, etched, polished to a mirror on one side, cleaned, and shipped against a written spec. The spec is what you are actually buying. "Prime" means total thickness variation under about a micron, site flatness held to tens of nanometers over an exposure-field-sized area, a 1–2 mm edge exclusion zone outside which nothing is guaranteed, interstitial oxygen controlled to a narrow band, and a particle count in the low tens of adders above a few tens of nanometers. Flatness is a lithography spec rather than a mechanical one: a scanner focuses over a field a few centimeters across, so a wafer out of site flatness prints defocused features across whole die. A standard 300 mm wafer is 775 µm thick and costs $60–150, which makes it the cheapest thing in a leading-edge fab by a wide margin.

Silicon is the only semiconductor that arrives essentially defect-free at commodity prices, in unlimited quantity, at 300 mm diameter. Nothing else on this sheet comes close on any of those three. The weakness is that everything is set at the crystal: doping type and level are fixed when the ingot is pulled, so you cannot have a lightly doped device region over a heavily doped substrate, and bulk CMOS built on it is vulnerable to latch-up. The failure mode to watch is not the wafer breaking, it is a spec excursion you find three months later. A flatness or particle drift at the wafer vendor shows up as focus and defect signatures across every lot that ran on it, and by then the wafers are finished product.

Default to polished prime and only move off it when a device requirement forces you. If the doping the crystal gives you is the doping the device wants, buy prime. Go to an epitaxial wafer (002) when the device layer and the substrate need different doping, when a CMOS design needs latch-up immunity, or when an image sensor needs a surface with fewer crystal-originated defects. Go to SOI (003) when you need a buried oxide, either as electrical isolation for RF and FD-SOI or as the lower cladding of a waveguide. Buy 300 mm whenever your process is qualified there, because it gives 2.25 times the usable area of 200 mm for only slightly more processing cost per wafer. Stay on 200 mm when your process, your device physics, or your customer qualification lives there, and budget extra time for equipment, because the used 200 mm market has been tight since 2020.

300 mm polished prime $60–150 a wafer at 775 µm thick · 300 mm carries 2.25× the area of 200 mm · total thickness variation under roughly 1 µm, site flatness in tens of nanometers, edge exclusion 1–2 mm · global capacity roughly 9.6M 300 mm wafer starts a month in 2026 against more than 7.7M at 200 mm · five firms supply roughly 90% of the market · the G450C 450 mm consortium spent about $4.8B over five years and wound down at the end of 2016.

Shin-Etsu Handotai, SUMCO, GlobalWafers, Siltronic, and SK Siltron sell roughly 90% of the world's prime silicon, and the two Japanese firms alone hold more than half of 300 mm capacity. Concentration is high but the product is closer to a commodity than most steps on this sheet, so the risk is not a single supplier refusing to sell. It is that every fab qualifies each wafer vendor per process, and requalifying a substitute takes months of split lots. That turns a plant outage into a shortage: when the 2011 Tohoku earthquake stopped Shin-Etsu's Shirakawa plant, which then supplied a large share of world 300 mm wafers, customers could not simply buy elsewhere. Feedstock polysilicon is a separate and less concentrated market (Wacker, Hemlock, Tokuyama, OCI, plus large Chinese producers who mostly serve solar). Chinese wafer makers, mainly National Silicon Industry Group and TCL Zhonghuan, are scaling 300 mm and are the one part of this supply chain getting less concentrated rather than more.

Shin-Etsu Handotai and SUMCO (Japan), GlobalWafers (Taiwan, with a CHIPS Act-supported 300 mm fab in Sherman, Texas), Siltronic (Germany, with its FabNext plant in Singapore), SK Siltron (Korea). The G450C consortium at SUNY Poly in Albany was the industry's attempt at 450 mm; Intel, TSMC, Samsung, IBM, and GlobalFoundries funded it and no foundry has 450 mm on a roadmap today.

At $60–150 for a 300 mm wafer, the substrate is a rounding error at the leading edge: an N2 wafer sells for around $30,000, so the silicon it starts on is well under 1% of the price. At mature nodes the ratio is different but still small, a few percent of a $3,000 wafer. That is why wafer cost is almost never the lever anyone should pull, and why the interesting number is availability rather than price. The wafer makers run a capital-heavy, cyclical business with long-term supply agreements, and they went through a hard inventory correction in 2023–24 before AI demand pulled 300 mm capacity back up. If you are building a business on silicon, assume the substrate stays cheap and plentiful, then notice how differently the compound-semiconductor entries (019, 023) read, where the substrate is most of the cost and the whole constraint.

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An epi wafer is a polished prime wafer with a fresh single-crystal silicon layer grown on top of it, usually by CVD at 900–1,150 °C (manufacturing-processes 190 covers the growth itself). The point is that the layer's doping is set by the gas rather than by the crystal, so it can differ from the substrate's by six orders of magnitude. People pay the premium for three reasons. A heavily doped substrate under a lightly doped device layer shunts the parasitic thyristor that causes CMOS latch-up. The grown surface has far fewer crystal-originated pits and oxygen-related defects than a polished surface, which matters enormously to image sensors, where a single defect is a visible bright pixel. And in a power device, the thickness and doping of a lightly doped drift layer are what set blocking voltage, so the epi spec is the device spec.

Epi gives you a doping profile no implant or diffusion can produce, over a surface cleaner than any polish, and it is a mature merchant product you can just buy. The costs are throughput and thermal budget: growth is slow and hot, so a reactor turns out far fewer wafers an hour than a polisher, and thick layers for power devices take proportionally longer. Two mechanisms fight you at the interface. Dopant out-diffusion and autodoping from the heavily doped substrate blur the junction you were trying to make sharp, which sets a floor on how thin a useful layer can be. The failure mode is thermal: a 1,100 °C process across a 300 mm disc creates radial stress, and if the ramp is wrong you get slip lines and stacking faults radiating from the wafer edge, which fail the wafer outright.

Buy epi when the device physics needs a doping profile the crystal cannot give. For advanced CMOS logic the decision is already made for you, since essentially all of it runs on epi. For an image sensor, buy epi for the defect surface and treat the specification of that surface as a yield decision. For a power MOSFET or diode above a few tens of volts, size the epi layer to your blocking voltage and expect thickness to run from a few microns for logic to tens of microns for a 1200 V silicon device. Skip epi for a plain mature-node digital or MEMS part that does not latch up and does not care about surface defects, because you are paying for something the device cannot use. If your drift layer is getting thick enough that on-resistance is becoming the problem, that is the signal to price silicon carbide (019) instead of more silicon epi.

Epi layer roughly 1–5 µm for logic against tens of microns for a 1200 V silicon power device · silicon CVD epitaxy grows at 0.1–5 µm/min at 900–1,150 °C · layer doping controllable from 10^14 to 10^20 cm^-3, independent of the substrate · epi reactors roughly $2–5M each · the same five firms that dominate polished prime (001) supply the merchant epi market.

Epi wafers come from the same five suppliers as polished prime, who grow the layer as a value-add step, plus a thin layer of specialist houses that buy prime wafers and sell epi. So the substrate concentration from 001 carries straight over, with one extra chokepoint on top: the reactors. Silicon epi tools are effectively a two-supplier market, Applied Materials and ASM International, and compound epitaxy is a separate duopoly in Aixtron and Veeco. Leading-edge fabs also run large in-house epi fleets, because epi is a device process step as well as a substrate purchase. SiGe source/drain stressors and the SiGe/Si superlattice that gate-all-around channels are cut from (015) are both grown in the fab, on the same class of tool. That means a restriction on advanced epi equipment hits a fab's device process, not just its wafer buying, which is why epi reactors sit inside the US advanced-equipment export rules rather than outside them.

Merchant epi from Shin-Etsu Handotai, SUMCO, GlobalWafers, Siltronic, and SK Siltron. Applied Materials' Centura epi platform and ASM International's Intrepid are the standard silicon epi reactors. Sony's CMOS image sensors, Infineon and onsemi power MOSFETs, and every advanced logic process at TSMC, Intel, and Samsung are built on epi substrates.

Epi is sold as a premium over polished prime, and the premium is real but poorly published, so treat any specific multiple you see with suspicion. What is safe to say is the shape: the adder scales with growth time, so a 3 µm logic epi layer is a modest uplift on a $60–150 wafer while a 100 µm power epi layer can dominate the substrate cost. That is the same mechanism that makes silicon carbide epi expensive in 019, just with a cheaper starting wafer and a faster growth rate. For a fab, the interesting question is make-or-buy: merchant epi is cheaper per wafer, captive epi gives you control of a process step that increasingly is the device. Advanced logic has answered that question by doing both.

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An SOI wafer is a thin single-crystal silicon film sitting on a buried oxide on a handle wafer, and it is built by layer transfer rather than by growth. Soitec's Smart Cut is the dominant route: implant hydrogen to a controlled depth in an oxidized donor wafer, bond the donor face-down to a handle wafer (manufacturing-processes 195), then anneal until the hydrogen-damaged plane splits and lifts off a film of exactly the implant depth, leaving the donor to be reclaimed and used again. Three different markets buy the result and are easy to confuse. RF-SOI puts a thin film over a high-resistivity handle so antenna switches stop coupling into the substrate. FD-SOI puts an undoped 6 nm-class film over a thin buried oxide so the channel is fully depleted and the back gate can be biased at runtime. Photonics-grade SOI is a 220 nm silicon device layer over roughly 2 µm of oxide, where the buried oxide is the waveguide's lower cladding rather than an electrical isolator.

The buried oxide removes substrate coupling and cuts junction capacitance, which is why RF-SOI switches are linear and low-loss and why FD-SOI gets FinFET-like leakage out of a planar process at planar-process cost, with body biasing as a knob you can turn after tape-out. Against that: the wafer costs a multiple of a bulk wafer, the oxide is a thermal insulator so devices self-heat, and the design ecosystem is thinner, with fewer foundries and fewer qualified IP libraries than bulk CMOS. The failure mode is film thickness uniformity. An FD-SOI channel is around 6 nm thick and has to hold roughly ±0.5 nm across a 300 mm wafer, because that variation lands directly on threshold voltage. A wafer vendor's uniformity drift becomes your device's Vt spread, and no fab process step downstream can correct it.

If you are building an antenna switch, tuner, or RF front-end module, RF-SOI is the default and there is not much of an argument left to have. If you need FinFET-class leakage but your volume cannot amortize a FinFET mask set and design NRE, FD-SOI at GlobalFoundries 22FDX or Samsung 18FDS is the deliberate decision not to go to the leading edge, and the body-bias knob is worth real power on a battery-powered part. If you are building silicon photonics, you buy photonics-grade SOI because the waveguide needs that buried oxide, and your substrate decision is made for you (029). Avoid SOI for thermally dense parts, where self-heating through the oxide hurts, and for cost-driven digital parts that run happily on bulk planar CMOS (013). Partially depleted SOI is legacy at this point; do not start a new design on it.

FD-SOI silicon film around 6 nm held to roughly ±0.5 nm across 300 mm · photonics-grade SOI at a 220 nm device layer over about 2 µm of buried oxide · RF-SOI went from under 20% of the antenna-switch market in 2010 to about 95% by 2016 · Soitec reports something over 70% share of RF-SOI · GlobalWafers' Smart Cut license was terminated, with a settlement transition running to June 2027.

This is the most concentrated substrate on the sheet. Soitec invented Smart Cut with CEA-Leti, owns the patent estate, and licenses it selectively; Shin-Etsu Handotai is the second qualified volume source, SUMCO makes bonded SOI, and Simgui in Shanghai holds a license for 200 mm. The supplier count is shrinking rather than growing: Soitec terminated GlobalWafers' license in October 2023, GlobalWafers litigated, and the July 2025 settlement ended the agreements with a transition period through June 2027. For photonics-grade SOI the count is one. Soitec is the only qualified volume supplier to Tower, GlobalFoundries, and TSMC, and requalifying a photonics substrate means requalifying the PDK built on it, which is a multi-year exercise rather than a purchasing decision. If you are building a silicon photonics business, that single supplier is a risk you have to write down explicitly.

Soitec (Bernin, France and Pasir Ris, Singapore) and Shin-Etsu Handotai on the substrate side. GlobalFoundries 22FDX and Samsung 18FDS and 28FDS on the FD-SOI side, with NXP and STMicroelectronics among the larger users. RF-SOI switches from Qorvo, Skyworks, and Broadcom sit in essentially every smartphone. GlobalFoundries Fotonix and Tower's photonics platform both run on Soitec photonics-grade SOI.

Engineered substrates sell at several times the price of a bulk wafer, and that spread is the whole business: Soitec runs specialty-materials margins on what is physically still a silicon disc, and it holds them because the process is licensed rather than copied. The exposure is end-market concentration. RF-SOI volume tracks smartphone units, which have been flat for years, so the growth case has moved to photonics-grade SOI on AI optical interconnect demand and to SmartSiC, the same layer-transfer trick applied to silicon carbide. For a chip designer the practical consequence is second-sourcing: an FD-SOI design has two credible substrate suppliers and two credible foundries, so treat a dual-source plan as something you have to engineer rather than something you can procure.

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An i-line stepper filters a mercury arc lamp down to its 365 nm emission line and projects a reticle image onto resist one field at a time, stepping across the wafer between exposures (manufacturing-processes 184 covers the resist process itself). It resolves roughly 350 nm, which sounds hopeless next to the rest of this part and is exactly what a large share of the world's silicon needs. A power MOSFET, an analog or mixed-signal part, a MEMS device, an LED, and a packaging redistribution layer all have minimum features well above that, and none of them get better if you print them finer. i-line also handles thick resists, tens of microns deep, that deep-UV tools cannot expose, which is what plating-based redistribution and MEMS structures require. The tool sells for around $3.8M against roughly $90M for an immersion scanner, and that ratio, not the resolution, is the reason it survives.

Everything about i-line is cheap and boring, which is the point: cheap tools, cheap masks, mature resists, no pellicle problems, high uptime, and a fleet that has been depreciating for decades. Against that, 350 nm is a hard floor, and depth of focus is shallow enough that wafer flatness and topography still matter. The real constraint is not the stepper's optics, it is the ecosystem around it. About 220 i-line steppers sold in 2024, so it remains a live product line, but the 200 mm tools that surround it — tracks, implanters, furnaces, metrology — have been scarce and expensive since 2020, and a mature-node fab expansion is more often gated by finding a used implanter than by lithography.

If your smallest feature is above roughly 0.35 µm, use i-line and stop looking. That covers power MOSFETs and IGBTs, most analog and mixed-signal, MEMS, LED and photonic device layers, image-sensor microlenses, and fan-out redistribution. If you are building on silicon carbide or gallium nitride, the device's performance comes from the material's breakdown field and mobility rather than from linewidth, so a finer scanner buys you nothing at all and you should spend the money on substrate and epi instead (019, 020). Move up to KrF (005) when a layer needs roughly 0.25 µm or below, or when your process has to run on 300 mm, since new i-line tools are a 200 mm-and-below product. Use direct-write laser or e-beam lithography instead only for one-offs and prototypes where you are trying to avoid a mask set entirely.

365 nm mercury i-line, resolving roughly 350 nm · about $3.8M average selling price across roughly 220 units sold in 2024 · against about €11M for a KrF scanner and roughly $90M for an ArF immersion scanner · resist thickness from under a micron to tens of microns · Nikon and Canon are the two suppliers of new tools.

Nikon and Canon build essentially all new i-line steppers; ASML left this segment long ago and does not want it back. Below the tool, every input is multi-sourced: mercury lamps, chrome-on-quartz masks, and i-line resists from Tokyo Ohka, JSR, Shin-Etsu, Sumitomo, Fujifilm, and Dow. There is also a deep secondhand market with brokers and refurbishers who will sell you a twenty-year-old stepper with a service contract. This is the one lithography rung where export control has no leverage: China's SMEE builds i-line tools domestically and they are good enough for this class of work, so a fully domestic Chinese power or analog fab is not a hypothetical. The practical bottleneck is the rest of the 200 mm line rather than the scanner, which is why used-equipment prices, not tool list prices, are the number to watch if you are planning mature-node capacity.

Canon's FPA series and Nikon's NSR i-line steppers are the two current product families. The fabs that run them are power and analog lines at Infineon, onsemi, Bosch, Rohm, and STMicroelectronics; MEMS lines at Bosch and ST; LED fabs across Taiwan and China; and the redistribution-layer lithography in fan-out packaging at ASE and Amkor (025).

At roughly $4M a tool running a hundred-plus wafers an hour, depreciation per wafer-layer is measured in cents, and a mask at this generation costs thousands of dollars rather than the hundreds of thousands an EUV reticle costs. That combination is what makes low-volume and long-lifetime products viable: an industrial sensor selling 50,000 units a year can amortize an i-line mask set, and cannot amortize anything above it. Tool prices here barely move from year to year and the installed base lasts decades, so the cost pressure on this rung comes from the device side rather than the equipment side. Chinese mature-node capacity has been driving down prices for exactly the parts i-line builds, which is a margin problem for incumbents and has nothing to do with lithography at all.

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KrF lithography uses a krypton fluoride excimer laser at 248 nm in a projection scanner, resolving roughly 110 nm in a single exposure (manufacturing-processes 184 covers the resist step). It is the workhorse of mature-node manufacturing and, less obviously, the tool that patterns most of the layers in a 3D NAND device. NAND stopped scaling sideways in 2013 and now scales by stacking layers, so a 300-layer part is built largely with 1990s-vintage optics plus one extremely hard etch (010) and a great deal of deposition. The economics follow from throughput: an ASML NXT:870B runs up to 400 wafers an hour against 220 on the best EUV tool, at a selling price around €11M against $180M and up. ArF dry at 193 nm sits between KrF and immersion at roughly 65 nm, but most new capacity skipped it and went straight from KrF to immersion.

KrF is fast, cheap per exposure, well understood, and supported by three tool vendors and a large secondhand fleet, which is a combination nothing above it offers. Deep-UV resists at 248 nm are mature and inexpensive. The limitation is that 110 nm is close to the end of what the wavelength and resist chemistry will give, so there is no meaningful extension path. The failure mode is the light source rather than the optics: an excimer laser chamber is a consumable with a defined pulse life, the gas has to be managed, and an unplanned chamber failure takes the tool down for a service visit. Cost of ownership at this rung is a laser service contract as much as it is depreciation.

If your features fall between roughly 110 nm and 350 nm, KrF is the cheapest tool that prints them, and it is the standard choice for mature logic, DRAM periphery, and the overwhelming majority of layers in a 3D NAND stack. Use i-line (004) instead for anything above about 350 nm, because the tool costs a third as much and the masks are cheaper. Go to ArF immersion (006) when a layer needs below about 110 nm, and expect to buy a 300 mm line to go with it. If you are planning capacity that must be buildable without an export license, KrF is the practical ceiling today, so design the process around what 110 nm plus etch and deposition can do rather than assuming you will get a finer tool later.

248 nm KrF excimer, resolving roughly 110 nm · about €11M average selling price · up to 400 wafers an hour on an ASML NXT:870B, against 220 on an EUV scanner · roughly $4M for the i-line rung below and $90M for the immersion rung above · three vendors still sell new tools, plus a deep used market.

This is the most competitive rung in lithography. ASML, Nikon, and Canon all still sell KrF scanners and there is a large secondhand fleet, so no single vendor can hold a fab hostage. One level down the picture tightens: excimer light sources come from Cymer, which ASML owns, and Gigaphoton, and KrF resists come from the same handful of Japanese chemical firms that supply everything else in this industry. Mask blanks are roughly 93% AGC and Hoya. The strategic point is what is not restricted. US and Dutch export rules cover EUV and advanced immersion tools but not KrF, so this is the finest lithography a Chinese fab can buy without a license, and it is also the rung China's own scanner program has publicly reached — SMEE ships KrF-class tools, while its 28 nm immersion tool has been announced repeatedly without a confirmed production shipment.

ASML's TWINSCAN NXT:870B, Nikon's KrF scanner line, and Canon's FPA-6300ES series. The 3D NAND fabs at Samsung, SK Hynix, Micron, Kioxia, and YMTC run large KrF fleets; so do mature logic lines at 90–130 nm, DRAM periphery layers, and CMOS image sensor fabs. SMIC's non-restricted capacity is built substantially on this generation.

At €11M and 400 wafers an hour, depreciation per wafer-layer is a few cents, and that is the number behind NAND's cost curve. Adding layers to a NAND stack adds deposition and etch time, not exposures, so cost per bit keeps falling on tools that were designed before anyone had heard of EUV. For anyone modeling mature-node economics, KrF capacity is cheap, available, and export-unrestricted, which is precisely why so much of it got built at once and why price competition at mature nodes has been severe. If your business plan depends on mature-node wafer prices holding, check how many KrF-based fabs are still under construction before you believe it.

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Immersion lithography fills the gap between the final lens element and the resist with purified water, whose refractive index of about 1.44 lets the system collect a wider cone of light and pushes numerical aperture from roughly 0.93 to 1.35. At 193 nm that gives 38 nm half-pitch in a single exposure, and nothing optical goes finer (manufacturing-processes 184 covers the underlying resist process). This is the most important tool in the industry by wafer count. Every leading-edge fab bought EUV and still runs the majority of its layers on immersion, because most layers do not need to be finer than 38 nm and an immersion exposure is far cheaper and faster than an EUV one. Anything below that floor has to be built with multi-patterning (007) or printed with EUV (008).

Immersion combines resolution, throughput, and overlay in a way nothing else matches: at least 295 wafers an hour on an NXT:2100i, with overlay of about 1.3 nm machine-to-machine and 1.7 nm on product, which is what makes multi-patterning possible at all. The resist, OPC, and mask ecosystem around 193 nm has had twenty years of investment. The weaknesses are the 38 nm floor and the water. Bubbles, watermarks, and material leaching out of the resist into the water all print as defects, and the immersion hood has to scan across the wafer at meters per second without leaving a droplet behind. Defectivity work on the water system is a permanent part of running these tools rather than a start-up problem you solve once.

If the layer prints at 38 nm half-pitch or coarser, expose it once on immersion and stop, because that is the cheapest way to get that resolution. If it prints finer, the decision is between multi-patterning and EUV, and you make it on cost per wafer-layer, cycle time, and edge placement error — EUV usually wins from about N7 down. Do not buy immersion for a line that KrF (005) can print, since the tool costs seven times as much and buys you nothing you will use. If you have no EUV access, immersion plus multi-patterning is the only route to an advanced node, and you should model the yield and cycle-time cost honestly rather than counting mask layers.

193 nm ArF with water raising numerical aperture to 1.35 · 38 nm half-pitch in a single exposure · at least 295 wafers an hour on an NXT:2100i · overlay about 1.3 nm machine-to-machine and 1.7 nm on product · roughly €83M per system, about $90M · ASML shipped roughly 130 immersion systems in 2025 against 48 EUV.

ASML is effectively the sole supplier. Nikon still builds immersion scanners and ships a handful a year, against ASML's dozens per quarter, and Canon never competed here, so a fab planning capacity has one realistic vendor. One level down, Zeiss SMT is the sole optics supplier and Cymer and Gigaphoton the light sources. Immersion is also where export control actually bites, which surprises people who think the rules are only about EUV: the Netherlands has required licences for advanced immersion tools since September 2023, and the MATCH Act introduced in April 2026 would bar immersion exports to any facility in China outright. ASML's China share of system sales fell from 36% in Q4 2025 to 19% in Q1 2026 as that regime tightened. There is no domestic Chinese alternative in production — SMEE's 28 nm immersion tool has been announced several times without a confirmed shipment — which makes second-hand immersion scanners the most contested capital good in the industry.

ASML TWINSCAN NXT:2100i and NXT:2050i; Nikon's NSR-S636E. Every leading-edge fab runs them, including TSMC, Samsung, Intel, SK Hynix, and Micron, usually for the large majority of their layer count. SMIC's 7 nm process is built entirely on immersion plus multi-patterning, which is the clearest demonstration of both what the tool can do and what it costs to push it that far.

Immersion is where ASML's unit volume and much of its installed-base service revenue come from, so the EUV headlines and the immersion cash flow are two different stories about the same company. Per wafer-layer, an immersion exposure is the cheapest fine-resolution step available, which is exactly why the multi-patterning-versus-EUV argument stays close and why extending low-NA EUV rather than buying High-NA (009) is a defensible position. For anyone tracking capacity: immersion shipments are a better proxy for total advanced wafer starts than EUV shipments are, because most layers on an advanced wafer are still printed this way.

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Multi-patterning is what you do when the pattern is finer than the light. Three families cover almost all of it. Litho-etch-litho-etch splits one design layer into two or more separately printed and etched masks that interleave, with triple and quadruple versions when two is not enough. Self-aligned double patterning prints a mandrel, deposits a conformal spacer over it by ALD (manufacturing-processes 193), etches the spacer back so it survives only on the mandrel sidewalls, removes the mandrel, and uses the remaining spacers as the mask, which halves the pitch and makes both edges of every line a product of one exposure. Self-aligned quadruple patterning runs that trick twice. Each family turns one design layer into several litho, deposition, and etch passes, so the wafer sees more steps rather than a better tool.

It works with tools you already own, which is the entire appeal, and the self-aligned variants actually beat the scanner's own overlay because a single lithography step defines both edges of a feature. The costs are cumulative and large. Litho-etch-litho-etch runs roughly 2.5 times the cost of a single exposure; an advanced node's mask set reached 60–100 reticles; and each pass adds queue time on top of process time, so cycle time stretches. The failure mode is edge placement error: two separately printed features have to land on each other, and when they do not you get shorts and opens that no amount of resolution fixes. Self-aligned patterning has a second constraint that shows up in design rather than manufacturing — spacers naturally produce regular gratings, so layouts become gratings plus cut masks, and the design rules tighten accordingly.

If the layer's pitch is finer than 38 nm half-pitch and you have no EUV, you have no choice, so the question is only which family. Use self-aligned double or quadruple patterning where the layout is a regular grating — fins, gate lines, lower metal levels — because the pitch control is better and the mask count is lower. Use litho-etch-litho-etch where it is not, and accept the overlay exposure. If you do have EUV, compare cost per wafer-layer directly: one EUV exposure typically beats three or more optical passes from about N7 down, which is the arithmetic that justified a $200M tool. If you are planning a fab without EUV access, this is your route to an advanced node, and you should model the yield loss and the throughput penalty rather than counting reticles and calling it a plan.

Litho-etch-litho-etch runs roughly 2.5× the cost of one exposure · self-aligned double patterning halves pitch per round and quadruple patterning quarters it · advanced-node mask sets reached 60–100 reticles · single-exposure floor of 38 nm half-pitch on immersion against about 13 nm on EUV · published estimates for an advanced-node mask set spanning about $10M to $30M.

Multi-patterning is a process rather than a product, so the supply question inverts: it multiplies demand for tools that already have several suppliers. Every added pass consumes another deposition chamber for the spacer film (Lam, ASM International, Tokyo Electron, Applied Materials), another etch chamber (Lam, Tokyo Electron, Applied Materials, and AMEC in China), and more metrology. Mask capacity is the one genuinely tight input: AGC and Hoya supply roughly 93% of mask blanks, and multi-beam mask writers come from IMS Nanofabrication and NuFlare. The strategic point is that multi-patterning converts capital and cycle time into resolution a fab cannot buy, and no export-control regime can close it, because every input has four or more suppliers and several have domestic Chinese equivalents. That is why restricting lithography slows an advanced node rather than stopping it.

Intel patterned fins and lower metal levels with self-aligned quadruple patterning at 14 nm and 10 nm. TSMC's original N7 shipped in volume with immersion multi-patterning before N7+ added EUV. SMIC's N+2 7 nm process, which shipped in the Huawei Kirin 9000s in 2023, is built this way. DRAM makers have used self-aligned double and quadruple patterning on active and bitline layers for years, and still do on the layers EUV has not reached (018).

The cost here is passes, not machines. Each pass adds tool time, mask cost, metrology, and another chance to create a defect, and cycle time is the underrated part: a wafer that spends longer in the fab ties up working capital and slows the yield learning that makes the next lot better. That is what made a $200M EUV scanner a rational purchase. It is also why denying a fab EUV makes it slower and more expensive rather than stopping it — SMIC's 7 nm parts are real and shipping, and while no reliable yield figure is public, the process is widely understood to run well below what an EUV-based flow achieves at the same node. If you are assessing a fab that patterns this way, ask about cycle time and cost per good die, not about whether it can print the feature.

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EUV lithography prints with 13.5 nm light, which is made by dropping molten tin into a vacuum chamber tens of thousands of times a second and vaporising each droplet with a CO2 laser so it radiates as a plasma. Everything downstream follows from the fact that EUV is absorbed by air and by glass: the whole optical path is multilayer molybdenum-silicon mirrors in vacuum, the mask is reflective rather than transmissive, and each mirror gives back only about 70% of what hits it, so a small fraction of the light the source makes reaches the resist. A 0.33 NA scanner prints about 13 nm half-pitch in a single exposure, which is what replaced three or four immersion passes at the tightest layers from roughly N7 down. The tool draws around a megawatt and costs roughly $180M for an NXE:3800E, with ASML's blended EUV selling price nearer €230M.

One EUV exposure replaces several optical passes, so it cuts step count, cycle time, and edge placement error at once, and that compound saving is why every leading-edge fab bought in. The weaknesses are capital cost, power, source availability, and stochastics. At these doses the number of photons landing in a single feature is small enough that shot noise produces random missing contacts and bridged lines — a yield loss you buy your way out of with more dose, which costs throughput, or with better resist chemistry, which is a slow research problem. Mask defectivity is the other failure mode. A single defect in a mask blank prints on every die on every wafer, and a pellicle that both survives EUV and transmits it is itself a hard engineering problem.

If a layer needs finer than 38 nm half-pitch and you can get a tool, compare one EUV exposure against three or more immersion passes on cost per wafer-layer, cycle time, and edge placement error. EUV usually wins from about N7 down, which is why adoption was universal among fabs that could buy one. Do not use EUV on layers immersion prints — nobody does, and a leading-edge flow still runs the majority of its layers on 006. If you are building memory that scales by stacking rather than shrinking, EUV buys almost nothing: 3D NAND's cost curve is decoupled from lithography entirely (017), and DRAM adopted EUV late and on only a few layers (018). If you cannot buy a tool, go to 007 and accept the cost.

13.5 nm light at NA 0.33, printing about 13 nm half-pitch in a single exposure · roughly $180M for an NXE:3800E, with ASML's blended EUV selling price around €230M · 220 wafers an hour at 30 mJ/cm², up from 160 on the NXE:3600D · source power about 600 W today, with 1,000 W demonstrated and 330 wafers an hour targeted for 2030 · roughly a megawatt of power per scanner · ASML shipped 48 EUV systems in 2025 and plans about 65 in 2026.

This is the most concentrated step in the industry and the reason export control works as a policy lever at all. ASML is the only company that builds a production EUV scanner, and no other country has reproduced one. Below ASML the chain is a series of single points: Zeiss SMT alone makes the mirrors, figured to sub-nanometer accuracy; Trumpf alone makes the CO2 drive lasers; Cymer, which ASML owns, makes the source; AGC and Hoya supply roughly 93% of mask blanks; and Japanese firms hold over 95% of high-end EUV resist. Every one of those would take a competitor a decade to replace. EUV has been unexportable to China since 2019 and no tool has ever been delivered there. Chinese programmes have produced laboratory sources and a steady flow of press reports about prototypes; none has produced a production scanner, and the mirror and source supply chain is a harder problem than the scanner itself.

ASML's NXE:3600D and NXE:3800E. TSMC has used EUV from N7+ through N5, N3, and N2; Samsung from 7LPP; Intel from Intel 4 onward and on 18A; SK Hynix and Micron on selected DRAM layers. The Dutch government's 2019 decision not to license a shipment to SMIC is the single clearest example of what sole-source supply means in practice.

Cost per wafer-layer on EUV is high, since you are depreciating a tool that costs $180M and up at 220 wafers an hour and feeding it a megawatt, and it still beats the multi-patterning it replaced at the tightest layers. ASML's position is the most defensible franchise in semiconductors, and the moat is a two-decade supply chain rather than a patent portfolio, which is why nobody has bought their way into it. For supply analysis, EUV shipments are the tightest available proxy for leading-edge capacity growth: 48 systems in 2025 and about 65 planned for 2026 puts a ceiling on how fast advanced wafer starts can expand, no matter how much capex anyone announces.

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High-NA EUV is the same 13.5 nm light through a much larger lens: numerical aperture rises from 0.33 to 0.55, and single-exposure resolution improves from about 13 nm to 8 nm half-pitch. The price of that aperture is anamorphic optics. To keep the angles at the reflective mask manageable, demagnification is 4× in one direction and 8× in the other, which halves the exposure field from 26 × 33 mm to 26 × 16.5 mm, or 429 mm². Any die larger than that has to be stitched from two exposures, with a seam that has to meet overlay spec and a floorplan built around it. The mirrors are the largest and most precise optics ever made for volume manufacturing, the system ships in a few hundred crates, and it lists at $350–400M.

The gain is that the tightest layers collapse from multiple patterned low-NA exposures back to one, which recovers step count, cycle time, and edge placement error the same way 0.33 NA EUV did against immersion. The costs are the price, the halved field, and the physics of higher NA: shallower depth of focus, thinner resists, and therefore more exposure to the stochastic defects that already limit low-NA EUV. The failure mode nobody had before is field stitching. A large accelerator or server die no longer fits in one shot, so the design has to be partitioned across a seam and the two halves have to align well enough that the circuits crossing it still work.

This is a live industry disagreement rather than a roadmap, and the arithmetic is simple enough to run yourself: one High-NA exposure costs roughly 2.5 times one low-NA exposure, so it only wins where it replaces more than two low-NA passes. Intel took the aggressive side. It took the first tool in Oregon in 2024, and in July 2026 it became the first company to ship a high-volume logic product with High-NA layers — a subset of Panther Lake, the Core Ultra Series 3, on 18A — with those layers dual-qualified on 0.33 NA tools as a hedge against tool availability. TSMC took the other side. In April 2026 it said A13 and A12, both due in 2029, will not need High-NA, on the argument that its team keeps finding ways to extend low-NA EUV and the tool is not worth its cost yet. If you are making this call, count the layers that genuinely need below 13 nm half-pitch, multiply by the pass count each way, then add defectivity and uptime — which are exactly the numbers neither company publishes.

NA 0.55 against 0.33, giving about 8 nm half-pitch against 13 nm · exposure field 26 × 16.5 mm, or 429 mm², half the standard reticle field · $350–400M a tool, with Samsung reported to have paid $773M for two · roughly 2.5× the cost of a low-NA exposure · fewer than about a dozen tools worldwide.

Sole source again, and tighter than 008. ASML is the only builder, and Zeiss SMT is the only source of the anamorphic mirror sets — hard enough that ASML took a 24.9% stake in Zeiss SMT in 2016 and funded the capacity to make them. Output is a handful of systems a year, so adoption is constrained by how many ASML can build as much as by whether fabs want them. Tool holders as of 2026 are Intel first, then SK Hynix, Samsung, and imec's joint High NA lab with ASML in Veldhoven. High-NA falls under the same export regime as 0.33 NA EUV and has never been exportable to China. The practical consequence of one supplier with a handful of units a year is that being early is itself a strategy: Intel's argument for buying first is that learning on the tool compounds and cannot be bought later.

ASML's TWINSCAN EXE:5000 and the production EXE:5200. Intel's D1X development fab in Oregon holds the first systems and produced the July 2026 Panther Lake shipment on 18A; Intel 14A is planned to use High-NA more broadly. The imec–ASML High NA EUV Lithography Lab in Veldhoven is where most of the industry's non-Intel learning happens. TSMC's published A16, A14, A13, and A12 roadmap does not require it.

At $350–400M before installation, a single High-NA scanner costs roughly what a hundred i-line steppers cost, and the decision to buy one turns entirely on cost per wafer-layer rather than on capability. For ASML, High-NA is a revenue-per-unit story rather than a volume one, and low-NA EUV plus immersion will keep supplying most of the units for years. For anyone modeling the Intel and TSMC positions: both can be right for their own product mixes, since the crossover depends on how many layers a given design actually needs below 13 nm half-pitch and on resist and uptime numbers that move every quarter. The disagreement will be settled by defect density and cost per good die, and neither company will publish those either.

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High-aspect-ratio etch is the single hardest removal step in the industry, and it is what actually limits 3D NAND layer count. A channel hole has to go through a few hundred alternating oxide and nitride films — several microns of material at aspect ratios past 60:1, in holes roughly 100 nm across — and come out straight, round, and the same diameter top and bottom, repeated billions of times across a 300 mm wafer with no misses. This is the same physics as DRIE (manufacturing-processes 187) about two orders of magnitude harder, and it does not work the same way: there is no Bosch-style etch-passivate cycling here, just a continuously tuned high-energy plasma. The current answer is cryogenic etch, which chills the wafer far below room temperature so passivation sticks to the sidewall and the etch runs faster and straighter than it does warm.

Nothing else makes a 3D NAND stack or a modern DRAM capacitor, so on capability there is no competition. The costs are time and uniformity. An etch of this depth takes tens of minutes per wafer — Tokyo Electron presented a 10 µm-deep channel-hole etch in 33 minutes as a speed breakthrough — which is why a NAND fab buys so many etch chambers and why etch is its largest equipment line item. The failure modes are all geometric and all fatal to the string: bowing, where the hole balloons in the middle; twisting, where it wanders off vertical deep in the stack; incomplete etch at the bottom; and aspect-ratio-dependent lag, where the slowest holes on the wafer finish long after the fastest ones. Each one gets worse as the stack gets taller, which is the real reason layer count is hard.

You do not choose this, the architecture chooses it for you. If you are building 3D NAND above roughly a hundred layers or a DRAM capacitor at current pitch, HAR etch is the gating capability, and the layer count you can ship is set by how deep you can etch straight rather than by anything in the lithography module. When the stack exceeds what one etch can do, the answer is string stacking — etch two or three decks separately and align them (017) — which costs you an alignment step and a resistance discontinuity. If your structure is tens of microns deep in bulk silicon rather than through a stacked film, as with through-silicon vias and MEMS, use DRIE instead: it is a far more forgiving problem on far cheaper tools.

Aspect ratios past 60:1 in 3D NAND channel holes and past 100:1 in DRAM capacitors · a few hundred alternating oxide and nitride layers, several microns thick, in holes roughly 100 nm across · tens of minutes of etch per wafer, with 10 µm demonstrated in 33 minutes · etch clusters at a few million dollars each, bought by the dozen rather than singly · Lam the largest dry-etch supplier, with the top three at roughly 90% of the market.

Lam Research and Tokyo Electron are the two that matter for HAR dielectric etch, with Applied Materials third; Lam is the largest supplier and the three together hold roughly 90% of the market. Published shares for Lam alone run from about a third to more than half, depending on whether wet etch and clean are counted in the denominator, so treat any single figure with care. Lam has owned NAND channel-hole etch for most of a decade and Tokyo Electron has been taking share, winning process-of-record positions for cryogenic channel-hole etch for 2026, which is the first serious contest in that application in years. In China, AMEC builds credible dielectric etchers and is the closest thing to a domestic alternative at this rung, which is one reason etch is a harder thing to embargo than lithography. Cryogenic etch specifically is a policy target: the MATCH Act introduced in April 2026 would bar cryogenic etch exports to any facility in China alongside immersion lithography. Consumables are their own chain — fluorocarbon gases, high-purity helium, and chamber parts in silicon, quartz, and yttria coatings, most of which come from a short list of Japanese and US suppliers.

Lam's Akara platform and its Lam Cryo 3.0 process are the current cryogenic dielectric etch products. Tokyo Electron demonstrated a 10 µm-deep memory channel hole etch in 33 minutes aimed at stacks beyond 400 layers. The customers are the NAND lines at Samsung, SK Hynix, Micron, Kioxia, and YMTC, and the capacitor etch at all three DRAM makers.

Etch is the largest equipment category in a NAND fab and among the largest in wafer fab equipment overall, and HAR etch is most of the reason. Every added deck adds etch time, so cost per bit keeps falling with layer count only as long as etch time per layer keeps falling with it. That race decides NAND's cost curve; lithography barely enters into it. For investors, Lam's revenue is more memory-levered than any other large equipment maker, which makes it the cleanest read on the NAND and DRAM capex cycle, and Tokyo Electron's cryogenic wins are the first credible threat to that position in years. For a fab operator, the number that matters is chambers per wafer start, because that is what an extra hundred layers actually costs you.

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Atomic layer etch removes material in self-limiting cycles instead of continuously, so the amount removed comes from the cycle count rather than from the time. One half-cycle modifies only the top atomic layer, usually by adsorbing chlorine or a fluorocarbon; the second half-cycle removes only the modified material, using ion energy set below the threshold that would sputter anything underneath. ALE is to plasma etch what ALD is to CVD, and manufacturing-processes 193 covers the self-limiting surface chemistry that both rest on. Removal per cycle is a fraction of a nanometer — Lam has published chlorine-argon silicon ALE at 1.2 Å per cycle with under 3% non-uniformity across a 300 mm wafer — which is the only practical way to release nanosheet channels without eating the sheets, trim fins and gates to within a few angstroms, and smooth the line-edge roughness EUV resists leave behind.

Precision and selectivity are the whole point, and both come from the same mechanism: if the removal step cannot touch unmodified material, then selectivity stops depending on rate ratios and starts depending on chemistry. The cost is throughput. Conventional reactive-ion etch removes nanometers a second; ALE removes about an angstrom per cycle with cycles measured in seconds, so it runs one to two orders of magnitude slower. The failure mode is incomplete saturation. If either half-reaction does not saturate everywhere — deep inside a high-aspect-ratio feature, or at the wafer edge — the process quietly stops being self-limiting and becomes an ordinary rate process with all the non-uniformity you were paying to avoid. Saturation time scales roughly as the square of the aspect ratio, which is why ALE and deep features (010) sit at opposite ends of the same toolset.

Use ALE where a few angstroms of error changes the device. Nanosheet channel release is the clearest case: SiGe has to come out from between silicon sheets a few nanometers thick, with enough selectivity that the sheets survive intact (015). Fin and gate trimming, recess etches specified as a thickness rather than a time, and post-EUV resist smoothing are the others. Everywhere else use conventional plasma etch (manufacturing-processes 186) and take the rate, because the throughput ALE costs you does not come back. A reasonable rule of thumb: if the tolerance on the step is a nanometer or worse, you do not need ALE and should not pay for it.

Roughly 1–2 Å removed per cycle, against conventional plasma etch rates of nanometers a second · under 3% non-uniformity across 300 mm in published silicon ALE · cycle times of seconds, giving one to two orders of magnitude lower throughput than continuous etch · saturation time scaling roughly as the square of the aspect ratio · Lam claims up to 3× throughput improvement with its DirectALE approach.

Four to eight firms can sell you something called ALE — Lam Research, Tokyo Electron, Applied Materials, and Hitachi High-Tech in production, plus Oxford Instruments and Plasma-Therm at research scale — which makes this look less concentrated than 010. In practice it is not much less. Only two or three of those have ALE qualified inside a leading-edge logic flow, and qualification is the real barrier: an ALE recipe is co-developed with a specific fab on a specific tool over years, and it does not transfer between vendors, so a fab's second source exists on paper long before it exists in production. Precursor gases come from the industrial gas majors (Linde, Air Liquide, Air Products, Taiyo Nippon Sanso) plus specialty houses supplying the thermal-ALE chemistries based on hydrogen fluoride and metal-organic ligand exchange. US rules on advanced etch equipment sales to Chinese leading-edge fabs cover ALE-capable tools, so the export exposure is the same as the rest of the etch category.

Lam's DirectALE and its published chlorine-argon silicon ALE at 1.2 Å per cycle. Nanosheet channel release at TSMC N2, Intel 18A, and Samsung SF3 all depend on it. So do fin and gate trimming at FinFET nodes, high-k and metal gate recess steps, and the resist-smoothing steps that make EUV line-edge roughness tolerable.

ALE is bought as a capability rather than as a tool category: it usually runs on the same etch platforms as everything else, with different hardware and different recipes, so the incremental capital is chamber count rather than a new machine on the floor. The cost shows up as throughput, and several times the chamber count for the same wafer starts is a real capex line. That is why vendors compete on ALE throughput rather than on precision, which everyone now has. For equipment demand: gate-all-around and backside power delivery both add ALE steps, so etch chambers per wafer start keep rising even when wafer volumes are flat, which is the structural reason etch has been gaining share of wafer fab equipment spending for a decade.

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The back end of line is the 15 to 20 levels of copper wiring that connect transistors to each other and out to the package, and it is where a modern logic die now loses most of its delay and much of its power. Each level is built by damascene: etch trenches and vias into a low-k dielectric, line them with a barrier and a copper seed, electroplate copper into them, and polish the overburden away (manufacturing-processes 194 covers the CMP step). The trouble is that the barrier does not scale. Tantalum nitride has to be a few nanometers thick whatever the wire is, so below roughly 20 nm wire width a growing share of the cross-section is barrier and liner rather than conductor. Copper itself also gets worse as it narrows: once the wire is comparable to the electron mean free path (about 40 nm in copper at room temperature), electrons scatter off sidewalls and grain boundaries and effective resistivity climbs steeply. Every fix so far is partial. Cobalt and ruthenium go into the tightest levels because they need a thinner barrier or none at all, porous low-k dielectrics around k = 2.5–3.0 and deliberate air gaps hold capacitance down, and the upper levels stay thick and wide to carry power.

Dual damascene is cheap, self-aligned between the via and the trench above it, and has thirty years of manufacturing learning behind it, which is why nobody has replaced it. The weaknesses are mechanical and electrical at the same time. Porous low-k is a weak, brittle film, so it cracks and delaminates under CMP downforce and again under the thermal stress a flip-chip package applies at the die corners, and porosity lets moisture and precursor gases in. The electrical failure mode is electromigration: at high current density, copper atoms drift with the electron flow and open a void at a via, which is a wear-out mechanism that shows up after months or years in the field rather than at wafer sort. That is why the current-density limit per wire, not the resistance, is often what sizes a power net.

You do not really choose this module. Every CMOS die above a couple of metal levels is built with damascene copper, so the decisions are how many metal levels to pay for, how aggressive to be on dielectric constant, and whether to buy cobalt or ruthenium at the tightest levels. If your design is wire-limited rather than transistor-limited, which most high-performance digital designs now are, spend the money there and look hard at backside power delivery (016) before you buy a lithography generation. If you are on a mature analog or power process at 180 nm and above, subtractive aluminum metallization is still cheaper and perfectly adequate, and thick top-metal aluminum is what carries the current in a power device anyway. Do not push to the most aggressive low-k available unless you have a packaging team that has already seen the delamination problem.

15–20 metal levels on a leading logic die · resistivity size effect below roughly 20 nm wire width · electron mean free path in copper about 40 nm at room temperature · low-k dielectrics around k = 2.5–3.0, plus air gaps · cobalt and ruthenium at the tightest levels, copper above them · world ruthenium supply roughly 30 tonnes a year, over 90% of it from South Africa.

The equipment side is comfortable by this sheet's standards. Barrier and seed PVD is dominated by Applied Materials, copper electroplating comes from Applied, Lam Research, and Ebara, low-k CVD from Applied and Lam, and CMP from Applied and Ebara. Four to eight credible suppliers means no single tool can stop a fab. The materials are tighter: CMP slurries come from Entegris, Fujimi, and Resonac, most polishing pads come from DuPont, and the metal-organic precursors for cobalt and ruthenium films come from a short list of specialty chemical firms including Merck KGaA, Air Liquide, and Adeka. The real concentration is in the metal itself. Ruthenium is recovered only as a byproduct of platinum-group mining, world supply is on the order of 30 tonnes a year, and over 90% of it comes from South Africa with most of the rest from Russia. Semiconductor demand is small against that today because ruthenium is used as a thin liner. If the industry moves it into the wires themselves at 2 nm and below, a market that cannot expand supply on its own starts to matter, and there is no second country to buy from.

IBM's CMOS 7S at 220 nm in 1997 was the first copper-interconnect logic process; TSMC's copper and low-k transition at 130 nm is what let it start winning leading-edge customers. Intel introduced air gaps at 14 nm and cobalt at its two tightest metal levels at 10 nm. Intel has also published a subtractive ruthenium scheme at sub-25 nm pitch reporting roughly 55% lower line resistance and 40% lower line-to-line capacitance than the damascene equivalent, and imec's interconnect program has driven most of the public work on ruthenium and molybdenum as copper replacements. Applied Materials' Endura platform is the standard barrier and seed tool.

Individually these are cheap tools. A plating or CMP system is a few million dollars against $90M or more for an immersion scanner, which is why the tool-cost tag here is low. The cost shows up in step count: every metal level is its own lithography, deposition, etch, plate, and polish sequence, so metal levels add cost linearly and a 15-level stack is a large fraction of the total steps on a wafer. The curve is going the wrong way. Levels keep increasing, the metals get more exotic, and the performance return per level keeps shrinking, because the resistance problem is set by physics rather than by process control. That is the reason backside power delivery (016) is worth its considerable trouble, and the reason interconnect research gets attention out of proportion to its equipment spend.

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Planar bulk CMOS is the ordinary flat MOSFET built directly into a doped silicon substrate: a well, an implanted source and drain, a thin gate dielectric, and a gate on top that controls the channel from one side only. It is the architecture most of the world's wafers still use, and it is what every cost-driven part gets built on. Scaling it stopped working somewhere around 28 nm, because a gate that touches only the top of the channel loses control of it as the gate gets shorter, and the leakage that follows rises exponentially rather than gradually. High-k metal gate at 45 nm and strain engineering bought a few more nodes, and then the industry stood the channel up as a fin (014). 28 nm was the last planar logic node with a broad customer base, and it has stayed the price and performance sweet spot for more than a decade.

The strengths are all economic and industrial rather than technical. Mask counts are low, the processes are decades old and yield well, dozens of companies can build them, and mature lines carry an enormous library of specialty add-ons that leading-edge processes do not offer: high-voltage devices, BCD for power management, embedded flash, thick copper for RF inductors, MEMS structures, and image-sensor pixels. The weakness is that a planar device below about 28 nm cannot hold the channel off. Subthreshold leakage climbs, and threshold voltage spreads out from device to device because the channel contains few enough dopant atoms that their random placement matters. The failure mode that ends the architecture is an SRAM one: as the threshold spread widens, some cells stop being reliably writable at the supply voltage the rest of the chip needs, so the memory fails before the logic does.

If the part is a microcontroller, a power-management IC, a display driver, an image sensor, an automotive sensor interface, or anything dominated by analog and I/O, stay on planar bulk at 28 nm to 180 nm and do not think about it again. A shrink has to be justified by performance now, because cost per transistor has been roughly flat since 28 nm: a 28 nm 300 mm wafer runs around $3,000 against about $30,000 at N2, and the density gain does not make up the difference. Move to FinFET (014) when you need modern CPU or GPU performance or the density of a large SoC. Move sideways to FD-SOI (003) when you want FinFET-like leakage and body biasing at close to planar-node cost, which is a common answer for battery-powered and RF-heavy parts.

28 nm as the last planar logic node with a broad customer base · about $3,000 for a 28 nm 300 mm wafer against roughly $30,000 at N2 · cost per transistor roughly flat from 28 nm onward · dozens of firms can manufacture here against three at the leading edge · Chinese fabs heading toward about 28% of world mature-node capacity.

This is the least concentrated technology on the sheet, and that is the whole point of it. i-line and KrF scanners come from Nikon and Canon as well as ASML, with SMEE building domestic Chinese equivalents; etch and deposition come from Applied Materials, Lam, and TEL, and increasingly from Naura and AMEC; and a large used-tool market supplies 200 mm lines that nobody builds new equipment for. No export-control regime bites at 28 nm and above. The exposure runs the other way. Western buyers depend on a mature-node supply base that is concentrating in China and Taiwan, and mainland Chinese fabs are heading toward roughly 28% of world mature-node capacity, built with state support and priced accordingly. If that supply is cut off or, more likely, floods the market, the damage is to the margins and survival of incumbent analog and power suppliers rather than to anyone's technical roadmap. The 2021–2022 automotive shortage was a mature-node shortage, not a leading-edge one, which is a fair preview of how this dependency actually hurts.

TSMC's 28HPC+ still runs large volumes more than a decade after introduction. GlobalFoundries built its business on 28SLP and 22FDX after leaving the leading edge. SMIC and Hua Hong have expanded mature-node capacity aggressively in China. Automotive and industrial microcontrollers from NXP, Infineon, STMicroelectronics, and Renesas are almost all planar, as are Texas Instruments' 300 mm analog lines in Texas and Utah, and the CMOS image sensors in every phone camera.

Most of this capacity is fully depreciated. A 28 nm line built between 2011 and 2015 has paid for its tools, so its cash cost per wafer is far below the price a new fab would need, and that is what makes mature nodes profitable and also what makes new entrants dangerous. China's buildout is the live variable: subsidized new capacity at mature nodes competes against depreciated Western capacity, and the winner of that fight is decided by pricing policy rather than by technology. If you are building a business here, the question to answer is not whether you can make the part but what your cost looks like when a competitor with state financing prices at cash cost. Tariff and Section 232 activity aimed at mature-node imports is the policy response, and it is unresolved.

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A FinFET stands the channel up as a thin vertical fin and wraps the gate around three of its sides. Because the gate is now close to the whole channel body instead of just its top surface, it regains electrostatic control at gate lengths where a planar device leaks, which let supply voltage keep falling and leakage stay bounded for another decade of scaling. Intel put it into production at 22 nm in 2011 with a 60 nm fin pitch and a 90 nm contacted poly pitch, TSMC and Samsung followed at 16 and 14 nm, and the architecture carried the industry all the way to 3 nm. Fins are not printed directly; they come from self-aligned multi-patterning (007), which is why fin pitch scaled faster than lithography did. The design consequence that matters most is quantization: a fin has a fixed effective width, so drive strength comes in whole fins and a designer picks one, two, or three of them rather than a width.

FinFETs deliver a much steeper subthreshold slope than planar devices, so the same leakage budget buys a lower threshold and a lower supply voltage, and drive current per unit of layout area went up because the fin is taller than it is wide. Ten years of volume manufacturing means the yields are excellent and the design ecosystem is complete. The architecture ran out for three reasons that compounded. Quantized widths make analog, I/O, and SRAM sizing awkward, and each node's fin depopulation (three fins per device down to two) made the granularity coarser. Parasitic capacitance between the gate and the source and drain epitaxy grew every node as pitches tightened, so the switching-speed gain kept getting eaten. And the gate never controlled the bottom of the fin well, so leakage flows underneath the channel unless you put a doped punch-through stop there, which degrades mobility in exchange.

If you are picking a node in 2026, FinFET is what you buy anywhere from 16 nm to 3 nm, and that covers most digital SoCs that are not chasing the frontier. The value point is the N7 and N5 family: the tools are depreciated, the design flows are mature, and the wafer costs roughly half what a 2 nm wafer does. Go to nanosheet (015) only when the last increment of performance per watt matters and your volume can amortize a 2 nm mask set and design NRE. Go back to planar (013) or FD-SOI (003) when the part is dominated by analog and I/O, because you will pay FinFET prices for transistors whose quantized widths make your analog blocks harder to design.

In production at 22 nm from 2011, with 60 nm fin pitch and 90 nm contacted poly pitch on that first node · used from 16 nm down to 3 nm · drive current quantized in whole fins, with fin count per device falling from three to two across nodes · three firms build it at 5 nm and below · SMIC reached 7 nm with DUV multi-patterning and no EUV · commonly cited design NRE of roughly $249M at 7 nm and $449M at 5 nm.

FinFET at 16 to 10 nm is an all-DUV technology: immersion scanners plus self-aligned multi-patterning, which is why SMIC could reach 7 nm without EUV, at a yield and throughput penalty. From 7 nm down, the tightest layers use EUV, and ASML is the only company on earth that builds one. The rest of the module list is a short oligopoly too: atomic-layer etch and deposition from Lam, TEL, Applied, and ASM International, and high-k metal gate ALD where ASM is unusually strong. Only TSMC, Samsung, and Intel run FinFET at 5 nm and below. GlobalFoundries stopped at 14 and 12 nm in 2018 and UMC never went past 14 nm, which is a reminder that the constraint is capital and learning rather than knowledge. The policy consequence is specific: cutting off EUV does not stop FinFET, because a determined fab can multi-pattern its way to 7 nm, which is why US export controls have moved toward immersion scanners and advanced etch rather than EUV alone.

Intel's 22 nm Ivy Bridge was the first tri-gate product. Apple's A9 in 2015 was dual-sourced across TSMC 16FF and Samsung 14LPE, which is the clearest side-by-side the industry has ever had. AMD's Zen line was built on GlobalFoundries 14 nm and then moved to TSMC N7. TSMC's N7, N6, N5, and N4 remain the volume workhorses for phone SoCs, GPUs, and networking silicon. SMIC's N+2 7 nm process in Huawei's Kirin 9000s in 2023 showed what multi-patterned FinFET looks like without EUV.

FinFET is where most leading-edge revenue still sits, and it will stay there for years because the N5 and N4 capacity is largely paid for while N2 capacity is not. The fixed costs are the whole story at this level: commonly cited estimates put chip design NRE at roughly $249M at 7 nm and $449M at 5 nm, so the node you can afford is set by your unit volume rather than by what the foundry offers. If you are shipping tens of millions of units at high ASPs, the leading edge pays; if you are shipping hundreds of thousands, a depreciated FinFET node almost always beats a newer one. The same logic is what pushed large designs into chiplets, where only the blocks that benefit sit on the newest node.

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A nanosheet transistor stacks two or three thin horizontal silicon sheets and wraps the gate around all four sides of each one, which is as much electrostatic control as you can get from a single channel. Getting there is a long process. Epitaxy grows an alternating SiGe and silicon superlattice, the stack is etched into a fin, cavities are etched back into the SiGe to form inner spacers, source and drain epitaxy is grown on the ends, and then the SiGe is removed by atomic layer etch (011) to release the sheets before the gate stack wraps them. The design win is that sheet width is drawn continuously rather than quantized in fins, so a designer sizes a transistor to what the circuit needs instead of rounding to the next fin (TSMC markets this as NanoFlex). All three leading-edge manufacturers are now in production on it.

At the same gate length a nanosheet turns off harder than a fin, which converts directly into either lower power or more performance. TSMC reports N2 at 35% lower power at the same performance or 15% more performance at the same power against N3E, and says N2 defect density came in below N3 at the same point in the ramp. Continuous width tuning also helps SRAM and analog, where fin quantization was always awkward. The weaknesses are process-control weaknesses, and they are severe. Inner spacers form inside a cavity nobody can inspect, channel release needs angstrom-level etch selectivity between SiGe and silicon across a whole wafer, and anything left behind between two sheets is a killer defect. The failure mode is a yield ramp that takes years instead of quarters: Samsung shipped SF3 first, in 2022, and had well-reported yield trouble for a long time afterward.

Pick nanosheet when you need the last increment of performance per watt and your volume can carry a 2 nm mask set and a design NRE commonly estimated around $725M. In practice that means large-volume phone SoCs, AI accelerators, and server CPUs, and very little else. If your bottleneck is memory bandwidth, packaging, or the thermal path rather than the transistor, the money buys more elsewhere, and 026 and 028 are where to spend it. If the bottleneck is power delivery and interconnect resistance, backside power (016) is the cheaper fix. Stay on FinFET (014) for anything cost-sensitive, and treat CFET as a 2030s question rather than a roadmap item you can plan around.

Two or three stacked sheets per device, with continuously tunable sheet width · TSMC N2 at 35% lower power at the same performance, or 15% more performance at the same power, against N3E · N2 defect density below N3 at the same point in the ramp · three firms in production: Samsung SF3 in 2022, Intel 18A in November 2025, TSMC N2 in December 2025 · about $30,000 for an N2 wafer · CFET around A7 in 2033 on imec's roadmap.

Two or three companies can build this, and they all depend on the same handful of tool vendors. EUV is required and ASML is the sole source; the superlattice epitaxy comes from Applied Materials and ASM; the channel release depends on atomic layer etch from Lam and TEL; the gate stack depends on ALD, where ASM International has an unusually strong position. Metrology is its own chokepoint, because the critical dimensions are now buried between sheets where a CD-SEM cannot see them, which pushed the industry onto scatterometry and X-ray techniques from KLA, Onto Innovation, and Bruker. No Chinese fab can build nanosheet at scale, because EUV cannot be exported there and multi-patterning at these pitches is impractical rather than merely expensive. If ASML stopped shipping EUV tomorrow, the leading edge would stop advancing everywhere at once, and there is no partial substitute at this node.

Samsung's SF3 entered production in 2022 and was the first gate-all-around logic process anywhere. Intel's 18A with RibbonFET went into production in November 2025 and ships in Panther Lake and Clearwater Forest. TSMC's N2 entered production in December 2025. imec's public roadmap puts forksheet as the next extension of nanosheet and CFET, which stacks the n-device over the p-device, at around A7 in 2033. Lam, Applied, and TEL all sell dedicated nanosheet release and inner-spacer process modules.

An N2 wafer runs about $30,000 against roughly $3,000 at 28 nm, and the extra process steps are the reason the tool-cost tag here is high rather than medium. What you get for it is real but incremental: a node's worth of power or performance, not a step change. The economics only work for products that either ship in enormous volume or sell for enough that a few percent of efficiency is worth hundreds of millions in NRE. That narrow customer list is the reason only three companies build at this level, and the reason those three are all betting that AI accelerator demand keeps their newest fabs full. If it does not, the depreciation on a leading-edge module is the fastest way to lose money in this industry.

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Backside power delivery moves the power distribution network off the front of the die and onto the back, so signal wiring and power wiring stop competing for the same congested metal levels. On a conventional die, thick low-resistance power rails have to come down through all 15 to 20 levels of interconnect (012) and end up right on top of the transistors, in exactly the layers where signal routing is tightest. The backside version bonds the finished wafer face-down onto a carrier, grinds the silicon away from its original 775 µm until the tips of previously buried nano-through-silicon-vias are exposed, and then builds the power metal on the newly revealed back surface. Signals keep the front-side stack, power comes up from behind, and the two stop interfering. It is the clearest case on this sheet of integration rather than lithography buying a node's worth of improvement.

Intel's published PowerVia test-chip results are about 30% less IR drop, 5–10% better standard-cell utilization, and up to roughly 4% more performance at constant power. TSMC claims 8–10% more speed at the same voltage or 15–20% less power at the same speed for A16 with Super Power Rail. Those are node-sized gains from integration, not from a smaller feature. The costs are all in handling a wafer that has been made structurally fragile. Bonding adds a step and a defect source, the thinning has to stop precisely at the nano-TSV tips across 300 mm, and the resulting stack warps enough that lithography on the backside needs die-by-die overlay compensation. The thermal path also gets worse, because heat that used to leave through bulk silicon now has to cross a metal stack. The expensive failure mode is that all of this happens after the front end is complete, so a thinning or bonding excursion scraps wafers that already carry their full processing cost.

Buy it when the design is power-delivery-limited: high-current, high-frequency CPU and GPU cores where IR drop already forces you to over-provision supply voltage, and where routing congestion in the lower metal levels is what your place-and-route team complains about. Do not buy it for low-power, analog-heavy, or thermally marginal parts, where the added process cost and the worse heat path buy nothing. TSMC's own N2X variant deliberately keeps front-side power for the highest-voltage high-performance segment, which is a useful signal that the trade is not universal. If interconnect resistance rather than power delivery is your problem, the cheaper answer is more or wider metal levels (012).

Wafer thinned from its original 775 µm down to the nano-TSV tips · Intel PowerVia at about 30% less IR drop, 5–10% better standard-cell utilization, and up to roughly 4% more performance at constant power · TSMC A16 at 8–10% more speed at the same voltage or 15–20% less power at the same speed · in production on Intel 18A from November 2025 · TSMC A16 slipped from late 2026 to 2027 · Samsung SF2Z targeted for 2027.

Two companies are in or near production and a third is close behind, and they share a narrow equipment base. Wafer-to-carrier bonding comes from EV Group and SUSS MicroTec, precision grinding and thinning from Disco and Okamoto with Disco holding most of that market, and the nano-TSV reveal depends on etch and CMP control from the same vendors as the rest of the back end. Backside lithography on a warped wafer is an ASML problem and an OPC problem at the same time. The awkward part is that this equipment is the same base technology advanced packaging uses for hybrid bonding (027), so leading-edge logic and packaging are now bidding for the same bonders and grinders from the same two or three suppliers, and that capacity is already tight. Nobody outside Intel, TSMC, and Samsung has both a leading-edge front end and a qualified bonding line, and there is no path to backside power without both.

Intel demonstrated PowerVia on the Blue Sky Creek E-core test chip in 2023 and shipped it in volume on 18A from November 2025, in Panther Lake. TSMC's Super Power Rail arrives with A16, whose volume production moved from late 2026 to 2027. Samsung has SF2Z on its roadmap for 2027. imec did much of the early public work on buried power rails and nano-TSVs that all three implementations descend from.

This adds steps to the most expensive wafers in the world, which is why the tool-cost tag is high. The argument for paying is straightforward: if bonding, thinning, and backside metal cost less than the next lithography generation and deliver a similar performance gain, you do it, and right now they do. The strategic argument matters more. Intel got here first and used it as the headline feature of 18A, which is the first time in a decade Intel has led on a process capability, and TSMC's slip means the gap is real for at least a year. For everyone else, the lesson is that the remaining gains at the frontier increasingly come from integration and packaging rather than from printing smaller features, and the companies that own bonding and thinning capability are positioned for both.

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NAND flash stopped scaling sideways around 2013 and started scaling upward instead. A 3D NAND array is a stack of alternating oxide and nitride films with vertical channel holes etched down through all of them, and every intersection of a hole with a word-line layer is one cell. Capacity comes from layer count, which has gone from 24 a decade ago to over 300 in production, with Samsung's tenth-generation V-NAND at 400. Two tricks made that possible. String stacking builds the array as two or three separate decks that are etched and aligned in sequence, because a single high-aspect-ratio etch (010) cannot get through the whole stack in one pass. And the CMOS periphery moved out from beside the array to underneath it or onto a separate bonded wafer (CMOS-under-array, and YMTC's wafer-bonded Xtacking), so control logic stops consuming die area that could hold bits.

The economics are the strength. Cost per bit falls with layer count, and layers cost deposition and etch time rather than lithography, so NAND's cost curve is decoupled from EUV entirely. This is the one high-density memory technology you can advance without ASML's hardest tool. The weaknesses are mechanical and thermal. A stack of several hundred alternating films carries enough intrinsic stress to bow a 300 mm wafer, channel holes taper and go out of round toward the bottom, each deck boundary is an alignment risk, and the etch runs tens of minutes per wafer, which is why a NAND fab buys an extraordinary number of etch chambers. The device-level cost of pushing capacity is QLC. Four bits per cell is 33% more capacity than TLC at the same array, paid for with endurance in the hundreds of program/erase cycles rather than the low thousands, and slower reads because more voltage levels have to be resolved.

NAND is the only viable bulk non-volatile storage at scale, so the real decision is bits per cell. If the workload is read-heavy and capacity-driven (AI training data sets, warm storage, read-intensive enterprise SSDs), QLC gives you the lowest dollars per terabyte and its endurance limit will not bind. If the workload writes constantly or cares about tail latency, pay for TLC, because a QLC drive that hits its endurance rating is a replacement rather than a repair. Do not design around NAND behaving like DRAM: read latency is microseconds rather than nanoseconds, and erase happens in large blocks, so the controller and the filesystem have to be built for it.

Layer counts from 24 a decade ago to over 300 in production, with Samsung's tenth generation at 400 · two or three decks per device · channel holes past 60:1 aspect ratio through several microns of stacked film · etch times of tens of minutes per wafer · QLC adds 33% more bits per cell than TLC, at hundreds rather than thousands of program/erase cycles · five firms make it.

Five companies make 3D NAND: Samsung at roughly 32% of the market in Q3 2025, SK Hynix at about 19% (with Solidigm), Kioxia at about 15% (with SanDisk), Micron, and China's YMTC. Equipment is more concentrated than the device makers are. Lam Research is the largest dry-etch supplier and, with TEL, effectively owns the high-aspect-ratio channel etch; deposition comes from Lam, Applied Materials, ASM, and Kokusai; and the wafer bonders that make Xtacking and bonded-array designs possible come from EV Group and SUSS MicroTec. Because none of this needs EUV, NAND is the technology where Chinese domestic capability goes furthest: YMTC was added to the US Entity List in December 2022 and has kept advancing anyway. That is exactly why US rules have targeted etch and deposition equipment for China alongside lithography. A Lam or TEL cutoff would stop a NAND roadmap; an ASML cutoff would not.

Samsung's V-NAND generations, now at 400 layers in its tenth generation. SK Hynix's 321-layer TLC. Kioxia and SanDisk's BiCS10 at 332 layers, which reaches over 37 Gb/mm² of areal density and beats higher-layer-count parts on density per layer. Micron at 276 layers. YMTC's Xtacking, which bonds a separately built CMOS wafer to the array wafer rather than building the periphery underneath it.

Cost per bit falls with layers, and the capital that buys layers is etch and deposition chambers rather than scanners, so a NAND fab's capex profile looks nothing like a logic fab's. That also makes the industry violently cyclical: capacity comes in large increments, bits per wafer jump with each generation, and prices have collapsed repeatedly when supply outran demand. The 2025 and 2026 memory upcycle has been driven more by DRAM and HBM than by NAND, and the capital that HBM is absorbing (018, 028) is capital not going into NAND layers. If you are building on NAND, assume the price per terabyte keeps falling on a multi-year trend and swings violently around it, and do not build a business that needs the trend line to hold in any given quarter.

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A DRAM cell is one transistor and one capacitor, and the capacitor is the hardest scaling problem in the industry. The stored charge has to stay roughly constant no matter how small the cell footprint gets, because the sense amplifier needs a detectable signal and the cell has to hold it for the whole refresh interval. Constant capacitance in a shrinking footprint means the capacitor grows taller, and aspect ratios are now past 100:1, etched and then filled with high-k dielectric and electrode films that have to be conformal all the way down. Node names stopped being nanometers for the same reason logic node names did: 1α, 1β, and 1γ correspond to roughly 14, 13, and 12 nm half-pitch, and the letters exist because the old labels had stopped tracking any physical dimension. Unlike NAND (017), DRAM has no production path to the third dimension yet.

DRAM is still the only memory with the latency, bandwidth, and effectively unlimited endurance that main memory needs, and the industry has kept cost per bit falling through pure process work rather than architectural change. The weaknesses all trace back to that capacitor. Tall, thin structures lean and touch their neighbours unless a support lattice holds them, so capacitor collapse is a real yield loss mechanism rather than a theoretical one. Refresh power grows as cells get leakier and more numerous. And crowding the cells worsens row hammer, where repeatedly activating one row disturbs charge in its neighbours, which is a security problem as much as a reliability one. The failure mode is charge loss: a cell that cannot hold its level for the refresh interval fails intermittently and at temperature, which is the worst kind of defect to screen for.

You do not choose whether to use DRAM, only how much and in what form. If bandwidth per watt is the binding constraint, as it is for any AI accelerator, you are buying HBM (028) and paying several times the per-gigabyte price of commodity parts. If capacity per dollar matters more, DDR5 and LPDDR are the answer and will stay so. The planning advice for 2026 is blunt: assume DRAM supply is set by HBM demand rather than by your own, because the same fabs make both and HBM takes priority. If your product's bill of materials assumes historical DRAM pricing, re-run it.

One transistor and one capacitor per bit · capacitor aspect ratio past 100:1 · 1α, 1β, and 1γ at roughly 14, 13, and 12 nm half-pitch · three firms make essentially all of it, with CXMT at about 7.7% share and targeting 10% by the end of 2026 · US rules since October 2022 require a license for equipment capable of DRAM below 18 nm half-pitch in China · HBM revenue roughly $35B in 2025 heading toward $60B in 2026.

Samsung, SK Hynix, and Micron make essentially all the world's DRAM, which makes this one of the most concentrated markets in manufacturing of any kind. CXMT is the only real fourth entrant, at roughly 7.7% of global share and targeting 10% by the end of 2026, and it is boxed in by two separate controls: EUV has been unavailable to it since 2019, and since October 2022 US rules have required a license for equipment capable of producing DRAM below 18 nm half-pitch in China. The result is a DUV multi-patterning process two to three generations behind the leaders. On the leaders' side, EUV is sole-sourced from ASML, and the high-k capacitor precursors come from a short list of specialty chemical suppliers. The US also restricted HBM exports to China in December 2024. What happens if a supplier goes down is not hypothetical: DRAM has no substitute, a single fab outage moves world prices within weeks, and the 2026 shortage has been the demonstration.

Samsung, SK Hynix, and Micron are all shipping 1γ-class nodes; Micron was the last of the three to adopt EUV, holding to multi-patterning through 1β and using EUV first at 1γ. SK Hynix supplies the majority of HBM, with its HBM4 base die built on a TSMC logic process rather than a DRAM one. CXMT's DDR5 has been validated by every major motherboard maker in 2026 while remaining hard to buy in the US. The 4F² cell with a vertical channel transistor and, later, 3D DRAM are the two directions everyone agrees are needed around 2030 and nobody has in production.

HBM now sets the price of everything else. An HBM bit consumes noticeably more wafer area than a DDR5 bit, because the die carries thousands of TSVs and a much wider interface and yields worse, so every wafer diverted to HBM removes more than its face value of commodity DRAM from the market. With HBM revenue running around $35B in 2025 and heading toward $60B in 2026, that diversion is large enough to have inverted the usual heuristic that HBM costs several times DDR5 per gigabyte. For anyone buying DRAM, the practical consequence is that supply is allocated by who is building AI systems, and for anyone selling it, this is the most profitable memory cycle in the industry's history. Both conditions are cyclical and neither should be extrapolated.

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With silicon carbide, the substrate is the product. SiC boules grow by physical vapor transport, subliming a powder source onto a seed at over 2,000 °C, at roughly 0.3–0.5 mm per hour, and they top out around 3–5 cm of usable length. Silicon pulls from a Czochralski melt at 1–2 mm per minute and yields ingots two meters long. That single comparison explains why a SiC wafer has always cost 30–50 times a silicon one. On top of the substrate goes an epitaxial drift layer whose thickness and doping set the blocking voltage, and then a device process that is completely unremarkable by logic standards. A 1200 V SiC MOSFET has feature sizes around a micron, so it is patterned on i-line steppers (004) of the generation logic fabs retired in the late 1990s, on 150 mm wafers. The performance comes from the material, not the linewidth: SiC's bandgap is about three times silicon's and its critical field about ten times, so the drift layer can be roughly ten times thinner and far more heavily doped for the same blocking voltage. That is why every compound-semiconductor entry on this sheet sits in the Mature node band, and it is worth being explicit about what that means. "Advanced semiconductor" and "leading-edge lithography" are different things, and a company can be at the technical frontier of power electronics while buying twenty-year-old steppers.

A thin, heavily doped drift layer means low on-resistance per unit area at 650–1700 V, and a majority-carrier device means no tail current, so switching losses are a fraction of a silicon IGBT's. SiC also conducts heat about three times better than silicon and works at junction temperatures silicon cannot reach. The weaknesses start with the substrate: it is expensive, it is small, and it carries defects that silicon does not, particularly basal plane dislocations that propagate into the epitaxial layer and cause the body diode's forward voltage to drift under bipolar conduction. The standing qualification worry is the gate oxide. The SiC and SiO2 interface has a high trap density and offers a lower barrier to electron injection than silicon's, so the failure mode is threshold voltage drift and eventual gate oxide breakdown after years of biased high-temperature operation. That is exactly the failure automotive qualification exists to catch and exactly the one that is hardest to accelerate honestly in a test.

If the system runs above about 650 V and switching losses dominate, SiC wins: EV traction inverters on 800 V architectures, DC fast chargers, solar string inverters, and rail traction. Make the case at system level, because you will not win it at the part. A 100 A SiC MOSFET still sells for roughly three times the equivalent silicon IGBT, and nobody credible expects device price parity; what pays for the premium is smaller magnetics, a smaller cooling system, and more range from the same battery. Below 650 V and above about 100 kHz, GaN (020) is usually the better answer. If the application is cost-driven, low-frequency, or runs at low duty cycle, a silicon IGBT still wins and probably always will.

PVT growth at roughly 0.3–0.5 mm per hour against 1–2 mm per minute for silicon · usable boule length 3–5 cm · SiC wafers 30–50× the price of silicon wafers · 150 mm substrates around $400 in 2026, after falling more than 60% through 2024 and another 40% in 2025 · devices at 650–1700 V · a 100 A SiC MOSFET at roughly 3× the price of an equivalent silicon IGBT · 200 mm under a few percent of shipments, forecast past 20% by 2030.

The substrate supplier list is short and it has changed hands fast. SICC, Wolfspeed, TanKeBlue, and Coherent lead it, with SK Siltron CSS, Resonac, and Rohm's SiCrystal behind them. Chinese suppliers went from roughly 10% of substrate revenue in 2021 to something like 40% in 2025, and SICC passed Wolfspeed for the top position. Device makers are a similarly short list: Infineon, STMicroelectronics, onsemi, Rohm, Mitsubishi Electric, Bosch, and Wolfspeed. What makes this entry different from the rest of the sheet is that the cutoff risk is inverted. PVT furnaces are not exotic, the process is well published, and the entry barrier turned out to be capital and patience rather than a tool nobody else can build, so the danger to an incumbent is being undercut rather than being denied supply. Substrate market revenue actually shrank 9% in 2024 to about $1.04B even as volumes grew, upstream utilization sat near 50%, and Wolfspeed went through Chapter 11 and emerged in September 2025 with debt cut about 70%. That is what commoditization looks like from the inside.

The Tesla Model 3 inverter, using STMicroelectronics SiC MOSFETs, was the volume proof point for automotive SiC; Tesla's 2023 statement that its next drive unit would use 75% less silicon carbide was an equally useful reminder that designers optimize hard when a part is expensive. Wolfspeed's Mohawk Valley fab and Infineon's Kulim expansion are the flagship 200 mm lines. SICC and TanKeBlue are building 200 mm substrate capacity in China with national fund backing. Chinese EV makers, BYD among them, have driven much of the recent volume.

The substrate has historically been the single largest line in a SiC die's cost, commonly put at around half, which is why the industry's whole cost roadmap is a substrate roadmap: bigger wafers, faster growth, better yield. The 200 mm transition is the main lever left, and it is still under a few percent of shipments with forecasts putting it past 20% by 2030. The 2024–2026 price collapse changed who can play. When 150 mm substrates fall from over $850 in 2023 to around $400 in 2026, a vertically integrated Western supplier that financed capacity at the old price is in trouble, and a subsidized new entrant with a fresh balance sheet is not. If you are evaluating a SiC business, the question is not whether demand grows, because it does, but whether the company's cost position survives another 40% substrate price decline.

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A power GaN device is a lateral high-electron-mobility transistor grown on an ordinary silicon wafer. There is no doped p-n junction doing the work. An AlGaN layer grown on GaN creates a two-dimensional electron gas at the interface through polarization, the electrons in that sheet are both dense and very mobile, and the gate depletes them to turn the device off. Growing GaN on silicon means bridging a large lattice and thermal-expansion mismatch with a stack of buffer layers, which is what limits how thick the GaN can be and therefore how much voltage it can hold. The economic argument is the entire point of the platform: it runs in existing depreciated 200 mm CMOS lines at roughly 98% line yield instead of needing a bespoke substrate, and Infineon produced the first 300 mm power GaN wafers with customer samples in late 2025, getting 2.3 times the die per wafer. Like SiC (019), the lithography is ordinary and the performance comes from the material.

A lateral GaN HEMT has very low gate charge and no body diode, so it has no reverse-recovery charge at all. That combination is what lets a converter run at hundreds of kilohertz to megahertz, where the magnetics and capacitors shrink by more than the semiconductor costs, which is why the phone charger got small. The weakness is structural. The device is lateral, so the drift region takes die area rather than die thickness, and every volt of blocking capability costs area. That caps the practical ceiling at about 650 V today and makes die area, not material cost, the binding constraint. There are two device-level catches worth knowing. Dynamic on-resistance rises when charge gets trapped in the buffer under hard switching, and most parts have no avalanche rating. The field failure mode follows from the first one: a design that met its thermal budget on the bench sees on-resistance drift up over months of hard-switched operation at high bus voltage, and the heatsink that was adequate stops being adequate.

Below 650 V and above roughly 100 kHz, GaN is the default now: chargers, adapters, and increasingly server and telecom power supplies. Above about 650 to 900 V, go to SiC (019), because the lateral structure runs out of area efficiency and you end up paying for silicon you cannot use. If the design is low-frequency and cost-driven, a silicon superjunction MOSFET is still cheaper and will stay cheaper. Do not pick GaN for high-current DC or low-frequency applications where conduction loss dominates and switching loss barely registers, because you are paying for a switching advantage you will never collect. And check the gate drive requirements early; p-GaN gate devices have a narrow drive window and are less forgiving than a silicon MOSFET.

Lateral HEMT with a 2DEG at an AlGaN/GaN heterojunction, and no body diode · practical ceiling about 650 V today · roughly 98% line yield in existing 200 mm CMOS lines · Infineon's first 300 mm power GaN wafers sampled in late 2025, at 2.3× the die per wafer · Innoscience at about 30% of the power GaN device market and gross-margin negative in 2024 · TSMC exiting GaN foundry entirely by July 2027.

Gallium is the exposure. China produced about 98% of the world's low-purity gallium in 2024, banned exports of it to the United States in December 2024, and suspended that ban in November 2025 through late November 2026, which means the constraint is currently a policy decision rather than a physical shortage. Epitaxy depends on MOCVD reactors from Aixtron and Veeco, with AMEC building domestic Chinese equivalents. The device supply base is unusually China-weighted for a Western-invented technology: Innoscience holds about 30% of the power GaN market from a 200 mm fab in China, and STMicroelectronics signed a GaN development and manufacturing agreement with it in March 2025. Meanwhile the foundry model is contracting. TSMC is out by July 2027, Navitas moved its foundry to Taiwan's PSMC in July 2025, and the industry is consolidating on integrated device makers (Infineon, Power Integrations, onsemi, Nexperia). Vertical GaN, which would need a bulk GaN substrate and would break the 650 V ceiling, has effectively failed as a category so far: NexGen went bankrupt and onsemi bought its fab for $20M, and Power Integrations absorbed Odyssey.

Phone and laptop chargers are the volume market, using parts from Navitas, Power Integrations, Innoscience, and Infineon. EPC's eGaN family put GaN into DC-DC and motor drive applications. Infineon's CoolGaN is the flagship of the 300 mm push. The market everyone is fighting for is data-center power, where 48 V architectures and the 800 V HVDC distribution NVIDIA has been pushing both favor GaN, with first commercial rollouts expected around 2027.

Prices are very low, and that is not an accident. GaN-on-silicon's whole pitch was that it uses cheap substrates in depreciated fabs, and a low barrier to entry is exactly what that produces. Innoscience holds roughly 30% share and was still gross-margin negative in 2024, which tells you what the price competition looks like at the top of the market. Because the device is area-limited rather than materials-limited, the only real cost lever left is wafer size, which is why Infineon's 300 mm move matters more than any device improvement on the roadmap. If you are evaluating a GaN business, the questions are whether it has a defensible wafer-cost position, whether it owns its fab, and whether it is exposed to a charger market where the customer switches suppliers over a few cents.

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This is the same AlGaN/GaN HEMT as the power device in 020, grown on a semi-insulating silicon carbide substrate instead of a silicon one. RF power amplifiers are thermally limited rather than voltage limited, and SiC conducts heat about three times better than silicon, so the same transistor can be driven far harder before the channel gets too hot. Production MMICs deliver roughly 4 W per millimeter of gate width at 10 GHz, research parts reach about 8 W/mm at 30 GHz, and laboratory devices have shown 30–40 W/mm; GaN-on-silicon's best is about 10 W/mm and only pulsed. The 3–4× gap in production parts is bought entirely with substrate thermal conductivity. Figures an order of magnitude above these circulate on market-report sites and are wrong. The lithography is as ordinary as in the other compound entries: gate lengths of 0.25, 0.15, and 0.1 µm are the standard production offerings, patterned on 100 and 150 mm wafers.

High power density means fewer devices, smaller combiners, and smaller amplifiers for a given output, which is exactly what an active electronically scanned array needs when every element has its own transmit chain. GaN's high breakdown field also lets the drain run at 28 to 50 V, which raises the device impedance and makes matching networks wider-band and less lossy than a GaAs part's. It tolerates load mismatch well. The weaknesses are cost and heat. Semi-insulating SiC is a different and scarcer grade than the conductive SiC that power devices use, wafers are 100 and 150 mm, and die cost stays high because of it. Thermal management remains the design constraint rather than a detail: reliability is specified as a mean time to failure at a stated channel temperature and qualified by extrapolating high-temperature operating life, so the failure mode is a thermal design that runs 20 °C hotter than the model assumed and loses most of the part's rated life without ever failing a bench test.

Choose GaN-on-SiC when you need watts of RF output above roughly 2 GHz and the thermal path is what limits you: radar transmit/receive modules, electronic warfare, satcom terminals, and macro-cell base stations. Use GaAs (022) for low-noise and small-signal functions and for handset power amplifiers, where GaN's cost and 28 V drive make no sense at all. Use GaN-on-silicon for lower-frequency, lower-power-density RF where cost matters more than watts per millimeter and you can spread the heat over more die. If the customer is a defense program, the deciding factor is usually not the datasheet. It is whether the fab holds DMEA trusted-foundry accreditation and whether the supply chain is ITAR-compliant, and that takes years to arrange and cannot be bought quickly.

Roughly 4 W/mm in production MMICs at 10 GHz · about 8 W/mm in research parts at 30 GHz and 30–40 W/mm in the laboratory · GaN-on-silicon's best about 10 W/mm and pulsed · gate lengths of 0.25, 0.15, and 0.1 µm on 100 and 150 mm wafers · RF GaN market about $2.0B in 2025, up from $740M in 2019, with military more than half of it · the top five vendors hold roughly 58–60% of revenue.

Semi-insulating SiC substrates come from a short list led by Wolfspeed and Coherent, with Chinese suppliers such as SICC and TanKeBlue moving in from the conductive-substrate side. Epitaxy needs MOCVD reactors from Aixtron or Veeco. On the device side, Qorvo, MACOM, NXP, Sumitomo Electric, and Mitsubishi Electric hold most of the merchant market, with in-house lines at RTX and Northrop Grumman and WIN Semiconductors serving fabless customers as a foundry; the top five vendors together are roughly 58–60% of revenue. MACOM bought Wolfspeed's RF business, including the 100 mm GaN fab at Research Triangle Park, for $125M in December 2023, which left Wolfspeed as a substrate supplier to its own former competitors. The binding constraint in this market is usually accreditation rather than capacity: defense programs need trusted-foundry status and long qualification cycles, which rules out most of the merchant world regardless of price. The material exposure is gallium, where China supplied about 98% of low-purity production in 2024 and restricted US exports in December 2024.

Raytheon's LTAMDS and Lockheed Martin's SPY-7 and LRDR radars are GaN-based AESAs, and the Patriot family's GaN upgrades are the clearest example of a fielded system re-hosted on the technology. Qorvo sells 0.15 µm and 0.09 µm GaN-on-SiC processes to fabless designers and to its own product lines. MACOM's RTP fab supplies defense and satcom parts. NXP and Sumitomo Electric supply the base-station side. WIN Semiconductors is the largest merchant compound-semiconductor foundry offering GaN-on-SiC alongside its GaAs lines.

This is not a price-competitive market, and the numbers show it. Revenue passed roughly $2B in 2025 from $740M in 2019, and military applications are more than half of it, so buyers are paying for qualification, supply assurance, and radiation and reliability data rather than for cents per die. Design cycles run years, volumes are modest, and there is consequently no pressure to move off 100 and 150 mm wafers even though die cost would fall on 200 mm. The telecom half of the market is the price-sensitive one, and it shrank when 5G macro build-outs slowed, which is why the mix tilted further toward defense. If you are looking at an RF GaN business, the durable asset is the accreditation and the qualified process, not the transistor.

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Gallium arsenide is the compound platform that already had its volume moment and is now defending it. Electron mobility is several times silicon's and the bandgap is direct, so GaAs does two things well: fast, low-noise, highly linear transistors for radio front ends, and efficient light emission. GaAs heterojunction bipolar transistors are still the standard cellular power amplifier, GaAs pHEMTs the standard switch and low-noise amplifier, and GaAs VCSELs light face-recognition sensors, optical mice, short-range LiDAR, and short-reach datacom links. The fab is defined by its epitaxy rather than its lithography. An Aixtron G10-class MOCVD reactor runs eight 150 mm wafers per batch for roughly €4M, 150 mm is the production standard, and the patterning is the same mature-node stepper work every compound platform uses.

The semi-insulating substrate gives low RF loss, the high mobility gives gain and low noise at frequencies where silicon struggles, and the direct bandgap gives efficient emitters at 850 to 980 nm. A real merchant foundry ecosystem exists too, so a fabless RF company can be built on it, which is not true of most compound platforms. The weakness is competitive rather than physical. GaAs is squeezed from both sides: RF-SOI (003) took antenna switches from under 20% of the market in 2010 to about 95% by 2016, CMOS power amplifiers take the low end of the handset market, and GaN-on-SiC (021) takes the high-power end. Thermal conductivity is about a third of silicon's, which limits power density. The failure mode is a business one. GaAs rarely loses a socket on performance; it loses when a silicon or SOI process becomes just good enough and the customer would rather integrate the function into a die it already buys.

Pick GaAs when you need linear RF power or low noise between roughly 0.5 and 100 GHz at handset cost and volume, or when you need an efficient emitter around 850 to 980 nm. Move to GaN-on-SiC (021) when you need watts of output and can pay for the substrate. Move to RF-SOI (003) when the function is switching or tuning rather than amplifying, because that battle is already over. Move to InP (023) when the light has to be at 1310 or 1550 nm, which GaAs cannot reach. The planning rule of thumb: if a CMOS or SOI process can plausibly meet the spec within two product generations, it will eventually take the socket, so treat a GaAs design win as defensible for a generation rather than permanently.

Electron mobility several times silicon's, with a direct bandgap · 150 mm as the production standard · an Aixtron G10-class MOCVD reactor at eight 150 mm wafers per batch for roughly €4M · RF-SOI took antenna switches from under 20% share in 2010 to about 95% by 2016 · mobile RF front end about $15.4B in 2024 · three substrate suppliers hold most of the GaAs wafer market.

Substrates come from Sumitomo Electric, Freiberger Compound Materials, and AXT through its Beijing Tongmei subsidiary, and those three hold most of the market between them, with Chinese suppliers expanding at smaller diameters. That AXT's crystal growth sits in China matters more than the corporate domicile suggests, because the feedstock is Chinese too: China produced about 98% of the world's low-purity gallium in 2024, banned exports to the United States in December 2024, and suspended that ban in November 2025 through late November 2026. Epitaxy depends on MOCVD reactors from Aixtron and Veeco. On the device side the merchant foundry model is genuine, with WIN Semiconductors the largest pure-play GaAs foundry and AWSC behind it, alongside integrated makers Skyworks, Qorvo, Sumitomo, and Murata. A gallium cutoff would not stop GaAs immediately, since substrate inventories and recycling absorb some of it, but there is no non-Chinese source at scale and no way to build one quickly.

Skyworks and Qorvo front-end modules put GaAs HBT amplifiers and pHEMT switches into most smartphones sold. Lumentum and ams-OSRAM supply the VCSEL arrays behind Face ID and consumer 3D sensing. WIN Semiconductors is the foundry behind much of the fabless RF world. AXT's Beijing Tongmei operation is the substrate supplier that ties the platform to Chinese export policy. Lumentum's conversion of a GaAs line to 6-inch InP is a useful signal about where capital thinks the growth is.

This is a large market that is not growing fast. The mobile RF front end was about $15.4B in 2024, and every new 5G band adds a socket GaAs can still win while RF-SOI and CMOS take the ones it already has, so the platform's revenue is a running battle rather than a trend. Capital intensity is modest by silicon standards. The expensive tool is a €4M MOCVD reactor, not a €90M scanner, so the business is decided by yield, packaging, and customer relationships rather than by who can raise the most capital. VCSELs are the growth line, tied to consumer 3D sensing and short-reach datacom, and both of those are volatile enough that a single phone design change can move a supplier's year.

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Indium phosphide is the only mainstream semiconductor that makes light efficiently at 1310 and 1550 nm, the two wavelengths silica fiber is transparent at, which is why every long-reach optical transceiver has an InP laser somewhere inside it. It is a direct-bandgap material, and the InGaAsP and InGaAlAs alloys that lattice-match to it let a designer place the emission wavelength exactly where the fiber needs it. The same platform makes the electro-absorption modulators and the fast photodiodes on either end of the link, and InP HBTs and HEMTs cover the highest-frequency analog work, including modulator drivers in the fastest optical links and mm-wave front ends. None of this needs fine lithography: devices are built on 2, 3, and 4-inch wafers with i-line and contact tools, because performance comes from epitaxial layer control rather than linewidth. What the platform does depend on is the substrate, and InP substrates are hard to grow. Crystals are pulled by liquid-encapsulated Czochralski or grown by vertical gradient freeze, they twin and crack easily, and single-crystal yields run around 20–25% against silicon's effectively perfect supply.

Nothing else does the job: InP emits at telecom wavelengths, detects at them, and can put laser, modulator, waveguide, and detector on one monolithic chip, with cutoff frequencies high enough for mm-wave work as a bonus. The weaknesses are all downstream of the crystal. Wafers are small and expensive, InP is more brittle than GaAs and much more brittle than silicon so handling losses are real, and it conducts heat roughly half as well as silicon, which limits how hard you can drive a laser. The failure mode to watch is not breakage during fab but slow degradation in the field: dislocations in the substrate propagate into the active region as dark-line defects, so substrate defect density sets laser lifetime, and a batch of marginal wafers shows up as field returns years later rather than as yield loss at test.

If the link runs over single-mode fiber past a few hundred meters, or the lane rate is 200 Gb/s and above, you need an InP source and you have no alternative. Use a monolithic InP photonic integrated circuit when the design is a handful of high-performance channels and you want the laser and modulator on the same die. If the design needs dozens of channels or a lot of passive routing (splitters, filters, switches), silicon photonics (029) gives better yield and wafer economics, and you attach an InP laser to it anyway. Below about 100 m over multimode fiber, GaAs VCSELs (022) are cheaper and good enough. In 2026 there is one more rule: check substrate lead times before you commit to a schedule, because InP supply, not design or fab capacity, is what is slipping optical module deliveries.

A 50 mm optical-grade wafer went from about $800 in early 2025 to $2,300–2,500 by April 2026, with spot quotes above $3,000 · demand ran more than 50% above supply · single-crystal yield roughly 20–25% · three firms hold over 90% of substrate capacity · China refines about 69% of the world's indium · 100–200 Gb/s per lane in shipping parts · moving from 3-inch to 6-inch wafers gives roughly 4× more devices per wafer and over 60% lower cost per chip.

Sumitomo Electric, AXT, and JX Advanced Metals hold more than 90% of InP substrate capacity, and all three are spending heavily to expand. The concentration is worse than a count of three suggests. AXT grows its crystals in China through its Beijing Tongmei subsidiary, and China both refines roughly 69% of the world's indium and added InP substrates to its export control list in February 2025, so two of the three exposures run through the same jurisdiction. Downstream, Lumentum has said it is shipping about 30% below customer demand and is converting a GaAs line to 6-inch InP, which is the clearest signal of where laser capital is going. If substrate supply is cut, there is no substitute at any price: silicon has an indirect bandgap and cannot lase, and GaAs cannot reach 1550 nm efficiently. The only real hedges are inventory, long-term supply agreements, and qualifying a second substrate vendor, which takes a year or more because laser reliability has to be requalified on the new material.

Lumentum and Coherent supply most of the world's transceiver lasers and EMLs. Infinera (now part of Nokia) built the largest commercial monolithic InP PICs, integrating dozens of functions on one chip for coherent line cards. SMART Photonics in Eindhoven runs an open InP foundry on a multi-project-wafer model, and Fraunhofer HHI does the same for research volumes. Substrates come from Sumitomo Electric, AXT (Beijing Tongmei), and JX Advanced Metals. On the analog side, Teledyne and Northrop Grumman use InP HBT and HEMT processes for mm-wave and sub-terahertz front ends.

The substrate is the cost, which is unusual for a semiconductor. A 2-inch InP wafer at $2,300–2,500 costs more than fifteen times what a 300 mm silicon wafer does, and it has about one thirty-fifth the area, so cost per mm² differs by more than two orders of magnitude. The fab steps that follow are cheap 1990s-vintage lithography by comparison. That makes wafer diameter the single biggest lever on device cost: the 3-inch to 6-inch transition is worth roughly 4× more devices per wafer and over 60% lower cost per chip, which is why every substrate maker is funding it. The 2025–2026 squeeze changed who captures the value. AI cluster optics pushed demand more than 50% above supply, prices roughly tripled in about a year, and margin moved upstream to the three substrate suppliers while module makers absorbed the increase. If you are building a business here, the question is whether you have contracted substrate supply through the expansion, because the expansions being funded now arrive in 2027 and 2028, and prices should ease when they do.

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This is the first-level interconnect decision, the one every chip makes before any of the exotic packaging on this sheet becomes relevant. Wire bond leaves the die face-up and runs a fine gold, copper, or palladium-coated copper wire from each perimeter pad to a lead frame or laminate substrate, one wire at a time. Flip-chip turns the die over, puts solder bumps across its whole face, reflows it onto a build-up substrate, and fills the gap with underfill. The difference that decides the choice is geometry: wire-bond pads live only on the die edge, so connection count scales with perimeter, while flip-chip bumps cover area, so connection count scales with the square of die size. Flip-chip also gives a much shorter path from the package to the die's power grid, which matters once current draw gets large. See manufacturing-processes 150, 151, 152, and 153 for how the bonding and encapsulation steps actually run; this entry is about which one to pick and what it costs.

Wire bond is cheap, mature, endlessly second-sourced, and reworkable in ways nothing downstream is, and a bonder that costs a few hundred thousand dollars will run for twenty years. Its ceiling is hard: at 40–60 µm pad pitch on the perimeter you top out in the low hundreds of connections, the wires add inductance that hurts at high frequency, and every amp of supply current runs down a long thin wire. Flip-chip buys thousands of I/O and a clean power path, and pays for it with an ABF build-up substrate that can cost more than the die on a mature part. Its characteristic failure mode is thermomechanical rather than electrical: the die and the organic substrate expand at different rates, so every power cycle works the solder joints and the underfill, and cracks show up at the die corners and in the substrate's low-k layers under the bumps. Warpage during reflow on a large thin package is the other one, and it gets worse as substrates get bigger.

Use wire bond whenever the part needs fewer than roughly 300 connections and is not power- or frequency-critical, which covers most microcontrollers, power ICs, sensors, and NAND. Use flip-chip once I/O count passes what the perimeter can hold, once supply current makes bond-wire inductance a power-integrity problem, or once the die is a processor of any kind. If the part is somewhere in the middle, price the substrate first, because the ABF build-up substrate rather than the bonding step is what makes flip-chip expensive at low pin counts. If flip-chip's substrate cost is the problem but you still need the I/O, look at fan-out (025), which deletes the substrate entirely. If you need a thousand-plus wires to a memory stack, neither of these reaches; go to 026.

Wire-bond pads at 40–60 µm pitch on the die perimeter, topping out in the low hundreds of connections · flip-chip C4 bumps at roughly 130 µm pitch across the die face, giving thousands of I/O · HPC substrates have gone from 3+3 to 13+13 build-up layers · Ajinomoto supplies over 95% of the ABF film those substrates are built from · wire-bond cost per die runs in cents, while flip-chip package cost is dominated by the substrate.

The assembly step itself is the least concentrated thing on this sheet. Dozens of OSATs will bond a die, led by ASE, Amkor, JCET, Powertech, and TongFu, and the bonder market has several credible vendors in ASMPT, Kulicke & Soffa, Besi, and Shinkawa. The concentration is one layer up, in the substrate. Ajinomoto supplies over 95% of the ABF dielectric film that every flip-chip build-up substrate is laminated from, which makes one Japanese chemical company a single point of failure for essentially all high-performance packaging, and the 2021–2023 shortage of it constrained the whole industry. The substrates themselves come from a short list (Ibiden, Unimicron, Shinko, AT&S, Nan Ya, Kyocera), and the highest-layer-count HPC substrates come from a shorter one, with Ibiden and Unimicron spending billions to add capacity. Glass-core substrates are the intended replacement and would move the chokepoint to glass makers such as Corning and AGC, but nothing has shipped in volume yet.

Nearly all NAND flash, microcontrollers, and power-management ICs ship wire-bonded, often as stacked die inside one plastic package. Every desktop and server CPU, GPU, and mobile application processor is flip-chip. Substrate suppliers include Ibiden and Shinko (long the Intel supply base), Unimicron, AT&S, and Nan Ya PCB. On the tooling side, ASMPT and Kulicke & Soffa dominate wire bonders. Intel's glass-substrate program and SKC's Absolics plant in Covington, Georgia are the two most visible attempts to replace the organic build-up substrate.

For a mature part, packaging and test together are roughly 15–20% of cost, and the wire-bond half of that is measured in cents. Flip-chip breaks that model because the substrate is a separate manufactured product with its own capacity cycle. An HPC substrate with 13+13 build-up layers is a hundred-plus-step process with its own yield problem, and during the 2021–2023 shortage it was the reason chips could not ship. Cost per connection is the number that decides the crossover: wire bond wins on total cost below a few hundred I/O and loses badly above it, since each additional wire is an additional second of machine time while each additional bump is free. The structural point for anyone investing here is that the assembly business is a commodity with many suppliers and thin margins, while the substrate business behind it is concentrated, capital-hungry, and periodically the binding constraint on the entire industry.

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Fan-out packaging deletes the substrate. Instead of bonding a die onto a laminate, you dice the wafer first, place only the known-good dies onto a carrier with deliberate gaps between them, mold the whole thing into a reconstituted wafer or panel, and then build the redistribution layers straight onto the molded surface. The gaps are what "fan-out" means: routing can spread past the die edge, so the package can have far more balls than the die has pads. Because the RDL is built with wafer-fab lithography rather than PCB-style laminate processing, it gets much finer than a substrate can manage, and because there is no substrate and no C4 bump, the package is thinner and the electrical path shorter. The two hard parts both come from the mold: dies move during compression molding and cure, and the reconstituted wafer warps because mold compound and silicon expand at different rates.

The RDL pitch is the headline. TSMC specifies 2 µm lines and spaces on InFO_oS against 5 µm and up for mainstream fan-out and far coarser on an organic substrate, so you get substrate-free routing density at lower cost and lower profile than flip-chip. It also integrates well: passives, multiple dies, and package-on-package memory all drop into the same flow. The weaknesses are the two mold problems. Die shift means each die ends up tens of microns from where you placed it, so a fixed RDL pattern no longer lines up, and the answer in production is adaptive patterning, where each die's actual position is measured and the exposure is adjusted per unit. Warpage limits how large and how thin a package can get, and it is the reason large fan-out parts need careful mold-compound selection and sometimes a stiffener. The failure mode when either goes wrong is an open or a shorted RDL trace at the die edge, found at final test after all the assembly money has been spent.

Pick fan-out when the part needs more I/O than wire bond can give but the flip-chip substrate is too expensive or too thick, which is exactly the mobile and RF situation. It is also the right answer when height matters, since deleting the substrate and the bump layer saves real millimeters in a phone. Use chip-last (RDL-first) if die cost is high and you cannot afford to lose good dies to RDL yield; use chip-first if throughput and cost matter more. Don't reach for fan-out if you need a very wide bus between a processor and memory stacks, because RDL alone will not carry a thousand-plus wires at the required density; that is 026's job. And if the design is a few hundred low-speed pins on a cost-driven part, wire bond (024) is still cheaper.

InFO_oS specifies 2 µm RDL lines and spaces, against 5 µm and up for mainstream fan-out · packages over 65 mm square in production · in every iPhone application processor since the A10 in 2016 · no organic substrate and no C4 bump in the stack-up · panel formats roughly 500–600 mm on a side, against a 300 mm round wafer, for better area utilization.

Fan-out is the least concentrated of the advanced packaging options, which is unusual and useful. TSMC's InFO is the highest-volume implementation, but ASE (FOCoS), Amkor, JCET, Powertech, and Samsung all run production fan-out lines, and Deca Technologies licenses the adaptive-patterning approach that solves die shift. The original eWLB process came out of Infineon and was licensed widely, which is a large part of why the supplier base is broad today. The equipment is also unremarkable: molding presses, i-line or KrF steppers for RDL, plating tools, and standard wafer-handling. What is genuinely scarce is process knowledge on warpage control at large package sizes, and panel-level capacity, where the tool sets are still being qualified. If you get cut off from one fan-out supplier you can usually qualify another in months rather than years, which cannot be said of anything in 026 or 027.

TSMC InFO has carried every iPhone application processor since the A10 in 2016, and InFO_oS extends it to packages over 65 mm square for networking and AI parts. ASE's FOCoS and Amkor's S-SWIFT serve the merchant market. Deca Technologies' M-Series with Adaptive Patterning is the standard answer to die shift and is licensed to several OSATs. Infineon's eWLB, licensed to STATS ChipPAC (now JCET), NANIUM (now Amkor), and ASE, is where the whole category started. Panel-level fan-out lines are running at Samsung, Powertech, and several Chinese OSATs.

Fan-out sits between wire bond and 2.5D on cost and captures most of the routing benefit of a substrate for less money, which is why it grew from a mobile niche to a mainstream option in about a decade. The economics are area-driven: everything is priced per unit of carrier area, so the cost lever is packing more dies onto one carrier, and that is the whole argument for moving from a 300 mm round wafer to a rectangular panel of 500–600 mm on a side, where edge waste is much smaller. Yield behaves differently than in front-end manufacturing, because a single bad die on a reconstituted wafer can lose you the RDL work spent on it, which is why chip-last flows exist and why known-good-die testing (031) is a precondition. For anyone building a business here, the honest read is that fan-out is a competitive market with many qualified suppliers, so returns come from process yield and panel-size transitions rather than from having a capability nobody else has.

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2.5D integration is how you run a thousand or more wires between a processor die and the memory stacks next to it, at a density no package substrate can reach. Two architectures do it. A silicon interposer, as in TSMC's CoWoS-S, puts every die on one continuous slab of silicon patterned like a chip, thinned to roughly 100 µm, with through-silicon vias carrying power and signal down to the package substrate. Embedded bridges, as in Intel's EMIB and TSMC's CoWoS-L, skip the full slab and drop small silicon bridge dies into an organic or molded interposer only where two chips need to talk. The bridge approach uses far less silicon for a given package area, and it scales further because the interposer is no longer limited by what a scanner can print. That does not make the finished package cheaper: CoWoS-L parts cost more per package than CoWoS-S because they are correspondingly larger, and what the bridge buys is the ability to build a package that a single stitched interposer could not reach at all. Both attach the dies with microbumps at 36–45 µm pitch, which is roughly three times finer than flip-chip C4 and about six times coarser than hybrid bonding (027). This is also the entry where the reader learns that packaging capacity, not wafer capacity, has been the binding constraint on AI hardware since 2023.

A silicon interposer gives you the shortest, densest, most predictable die-to-die wiring available short of bonding dies together, and it is the reason HBM works at all. It is expensive in a specific way: the interposer is a large piece of patterned silicon, so it is limited by the 858 mm² reticle field and has to be stitched from multiple exposures past that, and every square millimeter of it consumes 300 mm fab capacity that could have been product. Stitching to about 3.3 reticle fields is routine now, but interposer yield falls with area exactly the way die yield does, and a defect on a $750 interposer takes several $20,000 dies with it. Bridges avoid most of that by keeping the silicon small, at the cost of a harder assembly problem: the bridge has to be embedded flat and the dies have to land across a boundary between two different materials. The shared failure mode is warpage. These packages are large, thin, and made of materials with mismatched expansion, and warpage during reflow shows up as non-wet microbumps at the package corners.

Go to 2.5D the moment the design needs HBM, because nothing else carries a 1,024-bit or 2,048-bit interface at the required length. Below that, ask how many die-to-die signals you actually need: a few hundred fits on an organic substrate or fan-out RDL, a few thousand needs a bridge, and tens of thousands needs a full interposer. Choose bridges when the package is large and you want to avoid buying interposer area you do not use, and choose a monolithic interposer when die placement is dense and you want the simpler assembly flow. If the bandwidth requirement is higher still and the dies can be stacked rather than tiled, 027 gives roughly an order of magnitude more connections per mm² at lower energy per bit. And plan on lead times: CoWoS has been sold out since 2023, so capacity allocation is a commercial negotiation, not a purchase order.

Reticle limit 858 mm², with CoWoS-S stitched to roughly 3.3 reticle fields and CoWoS-L at 5.5 in 2026 · silicon interposer thinned to about 100 µm · microbumps at 36–45 µm pitch (EMIB 45 µm, EMIB-T validated at 36 µm, CoWoS microbumps around 40 µm) · TSMC CoWoS capacity from about 13k wafers per month at the end of 2023 to 35k in 2024 and 70–75k at the end of 2025, targeting 120–140k in 2026 · OSAT partners adding another 50–60k · package cost adder roughly $750 for CoWoS-S and $1,000–1,100 for CoWoS-L.

This is the tightest chokepoint in AI hardware right now, and it is not a tool problem. TSMC does the large majority of high-end 2.5D through CoWoS, Intel does EMIB in-house for its own products and a small merchant business, and Samsung's I-Cube is a distant third. Amkor, ASE and its SPIL unit, and KYEC take overflow chip-on-wafer and final assembly work, adding perhaps 50–60k wafers a month on top of TSMC's own capacity, but the interposer and the chip-on-wafer step still route through a short list. Capacity has been sold out continuously since 2023, so allocation, rather than price, is how supply gets rationed, and a startup without a committed slot generally cannot buy one at any price. The deeper reason a second source is hard is that interposer processing is 300 mm front-end work: you need a fab, not an assembly house, and TSMC's advantage is that it can convert its own capacity. If TSMC's packaging sites went offline, there is no configuration of the rest of the industry that replaces them inside a year.

NVIDIA's Hopper and Blackwell accelerators, AMD's Instinct MI300 series, Google's TPUs, and essentially every other HBM-equipped accelerator ship on CoWoS. Intel uses EMIB across Sapphire Rapids, Ponte Vecchio, and the Meteor Lake generation onward, often combined with Foveros stacking. Xilinx (now AMD) shipped the first commercial silicon-interposer product, the Virtex-7 2000T, in 2011, which is when the technology stopped being a research demo. Samsung's I-Cube and Amkor's S-Connect are the merchant alternatives.

The cost adder is roughly $750 per package for CoWoS-S and $1,000–1,100 for CoWoS-L, which sounds enormous until you compare it to the $20,000-plus of leading-edge silicon and HBM sitting on top of it. That ratio is why nobody optimizes packaging cost on an AI accelerator and everybody optimizes packaging availability. It also explains the industry's spending pattern: TSMC has been roughly doubling CoWoS capacity every year since 2023 and still selling it out, and the roadmap talk of 14 reticle fields with 24 HBM stacks by 2029 gets as much attention as the transistor roadmap. For anyone building here, the useful question is whether your product's constraint is wafer supply, packaging slots, or HBM allocation, because it has been packaging slots for three years running, and a design that needs less interposer area than a competitor's can ship in volumes the competitor cannot.

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3D stacking puts one die directly on top of another instead of tiling them side by side, and it comes in two rungs that are worth keeping straight. Microbump 3D, as in Intel's Foveros, solders a die onto the die below at 36 µm pitch, heading to 25 and 18 µm, and needs underfill in the gap. Hybrid bonding removes the solder entirely: both surfaces are polished flat, copper pads are recessed a few nanometers below the surrounding oxide, the oxide surfaces bond at room temperature on contact, and a subsequent anneal expands the copper across the gap so pad meets pad. With no solder ball and no gap to fill, pitch is set by lithography and alignment rather than by how small a solder joint can be made, which is why hybrid bonding runs at 6 µm today against 36 µm for microbumps. The connection is also shorter and has less capacitance, so it costs much less energy per bit. What it demands in exchange is a fab-grade surface: CMP-flat, particle-free, and placed to a couple of hundred nanometers.

The density gain is the point. TSMC claims up to 56× the interconnect density of 2.5D for SoIC, and the energy figure follows: roughly 0.05 pJ/bit for Foveros Direct against about 0.25 pJ/bit for a UCIe advanced-package link, which matters when a package moves tens of terabits per second. Stacking also shortens wires in a way no lateral arrangement can, which is why AMD's 3D V-Cache works. The costs are process discipline and heat. A single particle a few hundred nanometers across leaves an unbonded void, dishing from CMP leaves pads that never touch, and neither is reworkable, so the failure mode is a dead package containing several known-good dies. Thermally, stacking puts one heat source under another, and the die on the bottom is the one that cannot be cooled, which is why logic-on-logic stacking is usually arranged with the hot die on top. Throughput is the third cost: bonders run 1,600–2,000 die placements an hour, far below a conventional pick-and-place.

Stack when the two dies need to exchange more bandwidth than a lateral link can carry at acceptable energy, or when physically shortening the wire is the point, as with cache on top of a core complex. Use microbumps when the pitch you need is 25 µm or coarser, because the process is far more forgiving and runs in a normal assembly house. Move to hybrid bonding when you need single-digit-micron pitch, sub-0.1 pJ/bit links, or the thermal advantage of eliminating the underfill layer, and budget for the fact that your assembly step now needs cleanroom discipline and CMP. If the dies are large and mostly need to sit next to each other, 026 is cheaper and thermally easier. And check the thermal path before anything else, because on current AI parts the reason not to stack is usually heat rather than cost.

Microbump 3D at 36 µm pitch, heading to 25 and 18 µm · hybrid bonding at 6 µm today on TSMC SoIC, with 4.5 µm planned for 2029, and Intel Foveros Direct at 9 µm · up to 56× the interconnect density of 2.5D by TSMC's claim · roughly 0.05 pJ/bit for Foveros Direct against about 0.25 pJ/bit for a UCIe advanced-package link · die placement accuracy around 200 nm today, with sub-50 nm bonders arriving in 2026 · bonders run 1,600–2,000 die placements an hour.

Hybrid bonding is a two-supplier tool market at production quality. Besi, working with Applied Materials on the integrated flow, and ASMPT supply nearly all die-to-wafer hybrid bonders, with Hanmi trying to enter; EV Group and SUSS MicroTec dominate the wafer-to-wafer side. That is a narrower base than either the etch or the deposition market, and the tools are the gating item for every company that wants to build stacked products, so bonder lead times show up directly in product roadmaps. The intellectual property is concentrated too: Adeia holds the foundational hybrid-bonding patents from the Ziptronix work and licenses them broadly, which turned the technique into a royalty business with a stated path to $600M a year. The capability itself sits with three companies, since TSMC (SoIC), Intel (Foveros Direct), and Samsung (SAINT) are the only ones running it in volume, and each does it in-house. If you are a fabless company wanting hybrid bonding, your supplier list is your foundry.

AMD's 3D V-Cache stacks an SRAM die on a CCD with TSMC SoIC and is the highest-volume hybrid-bonded logic product. TSMC SoIC also underpins its 3DFabric stack and is used in AI accelerator designs alongside CoWoS. Intel's Foveros appears in Meteor Lake and Ponte Vecchio at microbump pitch, and Foveros Direct is its 9 µm hybrid-bonded version. Sony has used wafer-to-wafer hybrid bonding in stacked CMOS image sensors since the mid-2010s, which is where the technique got its first high-volume proving ground, and YMTC's Xtacking bonds a NAND array wafer to a CMOS logic wafer. Adeia licenses the underlying patents.

Hybrid bonding is cheap in materials and expensive in everything else. There is no solder, no underfill, and no bump plating, but you are adding CMP, cleanroom-grade handling, and a bonder that places dies at a fraction of conventional assembly throughput, so the cost per die placement is high and falls slowly. The business logic still works because the alternative is a bigger die or a slower link: stacking cache on a processor buys performance that would otherwise cost a node transition, and node transitions cost hundreds of millions in design NRE. Watch two things. The first is bonder throughput, since the current 1,600–2,000 placements an hour is the main obstacle to using hybrid bonding in high-volume memory, and it is the reason HBM has stayed with thermocompression and MR-MUF so far. The second is where the value accrues, which so far is the tool vendors and Adeia rather than the assembly houses, because the capability lives inside foundries that already own the customer relationship.

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High-bandwidth memory is DRAM sold as a packaging problem. Take 8, 12, or 16 DRAM dies, thin them to about 30 µm, run thousands of through-silicon vias straight down through the stack, and bond them onto a base die that talks to the processor. The result exposes a very wide, relatively slow bus instead of the narrow fast one a DDR module uses, which is how you get terabytes per second at tolerable power: signaling energy scales badly with frequency, so 1,024 wires at 10 Gb/s beats 64 wires at 160 Gb/s by a wide margin. The stack only works next to the processor, on an interposer or bridge (026), because a bus that wide cannot travel far. Two details define the current generation. The stacking method is still contested, with SK Hynix using mass reflow with molded underfill while others use thermocompression with non-conductive film, and the base die has moved from a DRAM process to a foundry logic process (TSMC N12 and N5 for HBM4), which turns the bottom of a memory stack into a logic chip.

Nothing else delivers this bandwidth per watt, and for an AI accelerator that is the entire ballgame, since the model weights have to come off memory faster than the arithmetic units can consume them. The costs start with area: the DRAM die carries TSVs and a very wide interface, so bit density per mm² is worse than commodity DRAM, and you are also buying interposer area and assembly. Capacity per stack is limited by how many dies fit inside JEDEC's 775 µm height allowance once they are thinned, which is the constraint that has driven die thinning to 30 µm. Thermally, HBM sits next to a kilowatt-class die and DRAM retention gets worse with temperature, so cooling design partly determines achievable speed. The failure mode that shapes the industry is unrecoverable: a stack is bonded, not socketed, so one bad DRAM die scraps eleven good ones and, if it is caught after assembly, an accelerator package worth thousands of dollars with it. That is why known-good-die testing (031) became mandatory rather than optional.

If you are designing anything that streams large working sets through a lot of arithmetic (training accelerators, inference accelerators, HPC processors, high-end networking), you need HBM and there is no substitute. If your workload is latency-sensitive rather than bandwidth-sensitive, or your working set fits in cache, HBM is a waste of money and package area; DDR5 or LPDDR gives you far more capacity per dollar. The real 2026 decision is usually not whether to use HBM but how much you can get: supply is allocated years ahead, three companies make it, and qualification with a given accelerator takes many months, so treat HBM allocation as a gating commercial item on the same footing as CoWoS capacity. If capacity per dollar matters more than bandwidth, look at conventional DRAM (018) and accept the bandwidth wall.

HBM3E runs a 1,024-bit interface at 9.2–12.4 Gb/s for roughly 1.2 TB/s per stack in 24 or 36 GB · HBM4 doubles the interface to 2,048 bits across 32 channels for about 2 TB/s at the JEDEC spec, with shipping parts at 10–11 Gb/s and Micron quoting over 2.8 TB/s · 8, 12, or 16 dies thinned to about 30 µm inside a 775 µm package height · HBM3E contract pricing has run around $13–17 per GB · HBM revenue roughly $35B in 2025 heading toward $60B in 2026 · SK Hynix holds something near 70% share.

Three companies make HBM: SK Hynix, Samsung, and Micron, and all three went into HBM4 production in early 2026. SK Hynix holds something close to 70% of the market, largely on the strength of its MR-MUF stacking process and its position as NVIDIA's lead supplier. That is a narrower base than DRAM generally, because HBM requires TSV processing, thinning, stacking, and qualification with a specific accelerator, and the qualification is the real barrier: a new supplier's parts take many months of joint work with the accelerator vendor before they ship. The chain has a second concentration point at the base die, which for HBM4 is manufactured by TSMC on a logic process, so a memory product now depends on leading-edge foundry capacity. HBM demand also sets DRAM supply for everyone else, because an HBM die spends area on TSVs and a very wide interface, so the same number of bits consumes considerably more wafer than commodity DRAM does. That is how AI spending ended up raising the price of laptop memory. Export controls apply directly: US rules restrict HBM shipments to China, making this one of the few finished components covered rather than a tool.

SK Hynix supplies most of the HBM in NVIDIA's H100, H200, and Blackwell parts and pioneered mass reflow with molded underfill. Micron's HBM3E and HBM4 lines ramped hard through 2025 and 2026. Samsung uses thermocompression with non-conductive film and returned to volume supply after well-publicized qualification difficulty. AMD's Instinct MI300 and MI350 series, Google's TPUs, and Intel's Gaudi parts all use HBM. On the standards side, JEDEC's HBM3E and HBM4 specifications define the interface width, height allowance, and speed grades that everyone builds to.

HBM inverted the usual memory business model. Commodity DRAM is a cyclical, undifferentiated product sold at spot prices; HBM is contracted a year or more ahead at negotiated prices, with margins several times higher, which is why SK Hynix's profitability diverged so sharply from the industry's historic pattern. HBM3E has been contracting around $13–17 per GB, and revenue is running roughly $35B in 2025 toward $60B in 2026. The old heuristic that HBM costs several times DDR5 per gigabyte stopped holding during the 2026 DRAM shortage, when commodity prices rose faster than contracted HBM prices. For anyone modeling an accelerator's bill of materials, memory is the largest line: across the 2025 volume mix, memory was about 63% of component cost against 15% for packaging and 13% for the leading-edge logic die. The chip everyone argues about is the cheapest part of the package.

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Silicon photonics builds waveguides, modulators, and germanium photodetectors in a standard CMOS fab, using the same lithography, etch, and deposition tools that make transistors, on SOI wafers (003) where the buried oxide confines the light. Co-packaged optics is the next step: put that photonic die in the same package as the switch ASIC or accelerator, so the electrical signal travels millimeters to the optical engine instead of tens of centimeters across a board to a pluggable module at the faceplate. The economic argument for the platform is that it inherits CMOS wafer scale, yield discipline, and 300 mm economics, which InP (023) cannot. The unavoidable catch is that silicon has an indirect bandgap and does not lase, so every platform still attaches or bonds an InP laser, either as a flip-chipped die or an externally coupled source. GlobalFoundries still lists on-die lasers as in development, and no one ships one.

Integration density and cost per function are the strengths: a single silicon photonic die can carry dozens of modulators, detectors, splitters, and wavelength filters, all patterned at CMOS yields on 200 or 300 mm wafers, which is why the platform won short- and medium-reach datacom. Co-packaging adds a real power argument, because pluggable optical modules consume a large and growing share of a switch's total power and most of that goes into driving a long, lossy electrical path that co-packaging shortens. The weaknesses are all about the laser and the field. The laser is a separate III-V die that has to be attached, aligned to sub-micron accuracy, and kept cool, and it remains the least reliable component in the assembly. Optical coupling in and out of the package needs fiber attach with its own alignment tolerance. The failure mode that actually slows adoption is serviceability: a pluggable module that fails gets swapped in a minute, while a failed optical engine inside a switch package means replacing the switch, so operators demand a reliability case that the industry is still building.

Use silicon photonics when the design needs many optical channels on one chip and cost per lane matters more than absolute per-lane performance, which describes datacenter interconnect. Use InP (023) instead when you need the highest per-lane performance, coherent long-haul optics, or a monolithic laser-plus-modulator on one die. Choose co-packaged optics when the electrical path is the power or reach bottleneck, which is now the case for high-radix AI-cluster switches, and stay with pluggables when serviceability, field-replaceability, and multi-vendor optics matter more than the power saving. If you are building the product, treat laser attach yield and the optical engine's field reliability as the two numbers your business case depends on, because everything else on the platform behaves like CMOS.

GlobalFoundries Fotonix in production at 100 Gb/s per wavelength, 200 Gb/s proven, 400 Gb/s in early access · 200 and 300 mm CMOS lines running standard fab tooling · zero on-die lasers, so every platform attaches or bonds an InP die · four or more merchant foundries with a silicon photonics process, against one qualified volume supplier of photonics-grade SOI · pluggable optics take a large and growing share of a switch's total power.

The fab side is comparatively healthy. GlobalFoundries, TSMC, Tower Semiconductor, Intel, and imec all run silicon photonics processes, so a designer has several credible foundries, which is more than can be said for most of this sheet. The concentration sits above and below. Below, Soitec is the only qualified volume supplier of photonics-grade SOI wafers to Tower, GlobalFoundries, and TSMC, so a platform that exists to escape III-V substrate risk depends on a single French substrate maker instead. Above, the InP lasers come from the same three-supplier substrate base described in 023, which means silicon photonics does not remove the InP chokepoint, it just shrinks how much InP each link needs. Packaging is the third constraint, since co-packaged optics needs advanced packaging capacity in the same queue as everything else in 026. If Soitec's photonics SOI line went down, the merchant foundries have no qualified alternative and requalifying one would take a year or more.

TSMC's COUPE program supplies the optical engines in NVIDIA's Quantum-X and Spectrum-X photonic switches, the first large-scale co-packaged optics deployment in AI networking. Broadcom's Tomahawk co-packaged switches are the other volume program. GlobalFoundries Fotonix is the leading merchant silicon photonics platform, with Tower's PH18 the other open foundry option. Intel shipped silicon photonics transceivers in volume for years before pivoting toward optical compute interconnect. Cisco (through Acacia and Luxtera), Marvell (through Inphi), and Ayar Labs are the visible merchant players, and Soitec supplies the photonics-grade SOI everyone builds on.

The pitch is that photonics becomes a CMOS cost curve rather than a III-V one, and to a real extent it has: a 300 mm silicon photonics wafer costs a small fraction of what the equivalent InP area would, and yield learning transfers from logic manufacturing. What has not become CMOS-like is assembly. Laser attach, fiber attach, and testing an optical part are per-unit operations with per-unit yields, so the cost curve flattens out in packaging even as the die gets cheap. That is why co-packaged optics has been on roadmaps far longer than it has been in products, and why the first volume deployments are in AI-cluster switches, where the power and reach benefit is large enough to justify a non-serviceable optical engine. The direction of travel is clear enough (per-lane rates from 100 to 200 to 400 Gb/s, optics moving from the faceplate into the package), but the honest read on timing is that adoption follows reliability data rather than the published roadmaps.

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A fab cannot improve a yield it cannot see, so at a leading node it measures something after a large fraction of its thousand-odd process steps. Two different jobs hide under the same heading. Metrology asks whether the process is on target: is the critical dimension what it should be, is the film the right thickness, did this layer land on the one below it? Scatterometry infers dimensions from how a periodic structure diffracts light, CD-SEM images features directly, and optical overlay tools read alignment marks. Inspection asks a different question, which is whether anything is there that should not be. Brightfield and darkfield optical scanners sweep a whole wafer looking for anything that differs from the neighbouring die, and e-beam review then goes back to the coordinates optics flagged and images them at resolution good enough to say what the defect actually is. Both feed the same loop: measure, find the drifting or failing step, correct it, and drive defect density down.

Process control is what makes a fab profitable rather than merely functional, because yield learning is the difference between a ramp that pays for the tools and one that does not. The fundamental limitation is a throughput-versus-sensitivity trade that has no way around it. An optical inspector scans a whole wafer but can only see defects near or above its wavelength, and turning up sensitivity slows it down and buries the engineer in nuisance detections. An e-beam tool sees essentially everything and inspects almost nothing per hour, so it is a sampling instrument, not a screen. The result is that no fab inspects everything, and the practical failure mode is a systematic defect that the sampling plan happens to miss, which then shows up weeks later as a yield cliff on lots already deep in the line. The second failure mode is a metrology tool that drifts, since a measurement error feeds straight into a process correction and moves the process off target with high confidence.

Every fab runs both, so the real decision is how much and where. As a rule of thumb, spend inspection capacity where a defect is both likely and fatal (lithography, high-aspect-ratio etch, CMP, and any bonding step) and spend metrology where the process window is tightest (overlay at multi-patterned layers, gate and channel dimensions, film thickness on anything conformal). Early in a ramp, inspect far more than makes economic sense at maturity, because the information is worth more than the throughput. Sample rather than screen once the process is stable and defect density has settled. If you are planning a fab, budget process control as a permanent operating capability rather than a startup cost, because a fab without inspection capacity cannot diagnose its own yield and will lose the learning race to one that can.

Defect density runs roughly 0.05–0.15 defects/cm² on a mature process against 0.2–0.5 early in a leading-edge ramp · a 1 cm² die at 0.1 defects/cm² yields about 90%, while a 6 cm² die at 0.4 yields under 20% · a leading-edge flow has something like a thousand process steps, with measurement after a large share of them · top-end patterned-wafer inspectors in the tens of millions of dollars each · e-beam review sees what optics cannot, at a small fraction of the area per hour.

Process control is the most concentrated equipment segment after lithography. KLA is the dominant supplier of patterned-wafer inspection and holds strong positions across metrology as well, with Applied Materials the main alternative in inspection and e-beam review, Hitachi High-Tech supplying most CD-SEMs, and ASML selling multi-beam e-beam inspection through its HMI unit. Onto Innovation, Nova, and Camtek fill out the optical metrology and packaging inspection tiers. Published figures for how much of wafer fab equipment spending goes to process control vary widely and are not worth quoting, but the concentration itself is not in dispute: for the highest-sensitivity inspection there is no broad second source. That has a practical consequence for anyone trying to build a fab outside the export-control perimeter, because inspection tools are on the restricted list alongside lithography and etch, and a fab that cannot inspect can still make wafers but cannot learn its way to competitive yield. Chinese suppliers such as Skyverse are the visible domestic effort, and they are furthest behind at the high-sensitivity end.

KLA's brightfield and darkfield patterned-wafer inspectors and its overlay metrology line are the industry references. Applied Materials sells the SEMVision e-beam review and Prizm CD-SEM lines. Hitachi High-Tech supplies most of the CD-SEM installed base. ASML's HMI multi-beam e-beam inspection tools target the sensitivity gap optics cannot close. Onto Innovation and Camtek dominate advanced-packaging inspection, where bump and RDL metrology on reconstituted wafers is a distinct problem. Nova supplies optical CD and materials metrology.

Process control tools do not add value to a wafer, which makes them permanently easy to under-buy and permanently the wrong thing to cut. The payback is entirely in yield learning speed, and yield learning speed compounds: a fab that finds a systematic defect two weeks earlier saves the material in the line plus the two weeks of ramp. That is why leading-edge fabs buy far more inspection per wafer start than mature ones, and why the segment's revenue tracks new-node ramps rather than total wafer volume. For investors the interesting structural feature is that the dominant supplier's position rests on defect-classification data and algorithms accumulated across decades of customer fabs, which is a harder thing to copy than a mechanism. Competing on the optics is possible; competing on knowing which of ten thousand detections matter is much harder.

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Wafer sort tests every die while it is still on the wafer, so that packaging money is only spent on dies that work. A prober steps the wafer under a probe card, the card lands thousands of needles or MEMS contacts on pads a few tens of microns across, and a tester exercises the die electrically and writes the result into a wafer map. Bad dies get inked or recorded and are discarded at dicing. This used to be a simple economic filter, worth doing because a package costs more than the test. Chiplets and stacked memory changed what it is for. When several dies are bonded into one package that cannot be reworked, sort is no longer screening out cheap losses, it is certifying that a die is good enough to bond, which is what "known-good die" means. The arithmetic behind that shift is the whole subject of this entry.

Sort is the cheapest place in the whole flow to find a bad die, since everything downstream adds cost you then throw away. Its limits are physical and statistical. Probing is a mechanical operation on a delicate surface, so pads get damaged, probe marks interfere with later bonding, and fine-pitch pads on a hybrid-bonded die may not tolerate probing at all. Test coverage at sort is also incomplete: the die is at wafer temperature, not at its operating temperature, and some failures only appear at speed in a real package. The failure mode that costs the most money is escape, a die that passes sort and fails later inside a bonded stack, which scraps every other die in the package. The opposite error costs money too, since tightening limits to catch escapes throws away good dies, and at leading-edge wafer prices a percentage point of overkill is expensive.

Every product gets sort; the decision is how much. Use light sort (a fast functional and continuity screen) when the package is cheap and the part gets a full final test anyway, which covers most mature-node products. Use full known-good-die testing, including at-speed and often at-temperature coverage, whenever the die goes into something unreworkable: an HBM stack, a chiplet assembly, a hybrid-bonded product. The test is economic, so run the numbers: if the value at risk in the assembled package exceeds the cost of deeper sort by a wide margin, test harder. On a 12-high HBM stack or a four-chiplet accelerator, it always does. If you are buying or selling chiplets, settle in the contract who eats the loss when a die that passed the seller's sort fails in the buyer's package, because that clause is now a real commercial term.

Four chiplets at 95% each give an 81% assembly · twelve DRAM dies at 99% each give an 89% stack · a twenty-die stack at 95% per die gives 35% · the probe-card market ran roughly $3B in 2025 · MEMS and vertical probe cards reach sub-40 µm and sub-20 µm pad pitch · HBM probing now runs above 3 GHz.

Probe cards are a consumable designed per product, which makes this one of the healthier supply positions on the sheet. FormFactor and Technoprobe lead a field that also includes Micronics Japan, Japan Electronic Materials, MPI, and SV Probe, so most designs have several qualified vendors, though the highest-frequency HBM and fine-pitch advanced-node cards come from a shorter list. Probers themselves are more concentrated, with Tokyo Electron and Tokyo Seimitsu holding most of the market. The genuine risk here is not being cut off but lead time: a probe card is custom to the die's pad layout, costs real money, and takes weeks to build, so a design change that moves pads has a schedule consequence most teams underestimate. Published unit prices for probe cards are unreliable enough that the useful planning number is the market size and the lead time rather than a price per card.

FormFactor's MEMS and vertical probe cards serve logic and DRAM sort, and its SUMMIT engineering probe stations are the lab equivalent. Technoprobe supplies a large share of the vertical probe cards used on advanced logic. Tokyo Electron's Precio and Tokyo Seimitsu's UF-series probers make up most of the installed prober base. On the buyer side, every HBM vendor runs full known-good-die and known-good-stack testing before bonding, and AMD, Intel, and the AI accelerator vendors all specify chiplet-level KGD criteria to their foundries and OSATs.

The cost of sort is machine time, and machine time is priced per second, so the lever every test engineer pulls is test time per die and how many dies can be tested in parallel. Memory sort runs hundreds of dies at once because the patterns are regular; complex logic parallelizes far less, so its sort cost per die is higher. The compound-yield arithmetic is what has changed the spending. At four chiplets and 95% each you lose 19% of assemblies; at twelve dies and 99% each you lose 11% of stacks, and each scrapped stack contains eleven good dies. Once a package holds $2,000 of silicon, spending several extra seconds per die at sort is obviously correct, which is why test spending per part has been rising for exactly the products where packaging costs the most. It is also why the probe-card business grew into a $3B market: cards for HBM and advanced logic are more complex, wear out, and get redesigned every product generation.

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Heterogeneous Integration Roadmap 2025, Chapter 17: Test Technology (IEEE Electronics Packaging Society)

Final test is the last gate, and it runs on the packaged part rather than the wafer, which is why this is the one entry on the sheet with no wafer tag. Three things happen here and they answer different questions. Automated test equipment exercises the device at speed, at voltage, and across temperature, running structured patterns (scan, memory BIST, analog and RF measurements) to prove the circuit is electrically correct after assembly. Burn-in runs the part hot and biased for hours to force early-life failures out before shipment, which is how automotive suppliers get to single-digit defective parts per million. System-level test boots the part in a board that resembles its real application and runs real software, because high-end SoCs fail in ways that structured patterns do not model, particularly marginal timing and power-management interactions. Everything here is priced in seconds of machine time, so the whole discipline is a negotiation between coverage and cost.

Final test is the only place that sees the finished product, so it catches assembly defects, package parasitics, and interactions that no wafer-level test can reach, and it is the last chance before a defect becomes a customer return. It is also, unavoidably, a throughput bottleneck: test time is serial per socket, so a part with a two-minute test needs a lot of testers to support high volume, and testers are capital equipment sitting between the factory and revenue. Burn-in adds hours of dwell time and its own oven capacity. System-level test adds the most coverage per second for complex SoCs but is the hardest to automate and to correlate, since a failure in a real workload does not always point at a circuit. The failure mode worth naming is a test escape on a part that ships: at automotive or datacenter volumes, a defect rate measured in parts per million turns into a recall or a fleet-wide reliability problem, and the cost of that dwarfs the test time you saved.

Everything gets final test. Add burn-in when the application cannot tolerate infant mortality, which in practice means automotive, medical, aerospace, and some datacenter parts, and skip it on consumer parts where the field return cost is lower than the oven time. Add system-level test when the part is complex enough that structured coverage leaves real risk, which today means high-end SoCs, accelerators, and anything with a lot of power-management state. The rule of thumb for the trade is simple arithmetic: a tester at $100 an hour makes one second of test time worth about 2.8 cents per chip, so compare the marginal test seconds against the escape rate they buy down times the cost of an escape. If you are budgeting a program, use 2–3% of device cost as the historical benchmark and expect 3–5% for large AI parts with long test times.

Test has historically been managed to about 2–3% of device cost, rising toward 3–5% for large AI parts, rather than the 5–10% that is often quoted · a tester at $100 an hour makes one second of test time worth about 2.8 cents per chip · modern high-speed ATE systems cost $1–3M each · Advantest and Teradyne hold roughly 80% of the market between them · Advantest's SoC tester share rose to roughly two-thirds in 2025 on AI demand · burn-in runs hours at elevated temperature and bias, which is how automotive parts reach single-digit defective parts per million.

Two companies, Advantest and Teradyne, hold roughly 80% of the automated test equipment market between them, and Advantest's share of SoC testers specifically rose to about two-thirds during 2025 as AI parts with long test times pulled demand its way. Cohu, Chroma ATE, and a handful of Chinese entrants make up most of the rest, mainly at the lower-performance end. Around the tester sits a second tier that is easier to source: handlers, thermal control units, burn-in ovens, and load boards come from many suppliers, and the test houses themselves (KYEC, ASE, Amkor, and the captive lines at every IDM) compete openly. The exposure to watch is therefore capacity rather than access. Testers are built to order with long lead times, and when AI demand spiked, tester delivery slots became a real constraint on how fast accelerators could ship. ATE also falls under export controls for advanced applications, though less tightly than lithography, so the practical risk for a Chinese buyer is buying older or domestic equipment and paying for it in test time.

Advantest's V93000 platform and Teradyne's UltraFLEX family cover most high-end SoC and accelerator test. Both also sell dedicated memory testers, including Teradyne's Magnum line, where hundreds of devices are tested in parallel. Cohu supplies testers and much of the handler and contactor market. King Yuan Electronics (KYEC) in Taiwan is the largest independent test house and does a large share of AI accelerator final test. On the buyer side, automotive suppliers such as Bosch, Infineon, and NXP run burn-in and extended-temperature programs to hit their parts-per-million targets, and Apple, NVIDIA, AMD, and Intel all use system-level test on their highest-end parts.

Test is a small share of device cost and a large share of the argument, because it is one of the few places a program manager can visibly cut. The defensible figures are roughly 2–3% of device cost historically, rising toward 3–5% for large AI parts, which is well below the 5–10% that circulates in secondary sources. What is changing is the direction: test time per part is growing because dies are larger, packages contain more dies, and system-level test is spreading down from the highest-end products, while the cost per test second is falling only slowly. That combination is why Advantest's revenue tracked the AI buildout so closely in 2025 and why its guidance rose sharply mid-year. For anyone building a business here, the durable positions are the tester platform itself, which is a duopoly with a decades-long software and applications moat, and independent test capacity, which is a capital-intensive service business that gets pricing power exactly when the industry is capacity-constrained.

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VLSI Test Process and Test Equipment, ET4076 Lecture 2 (TU Delft OpenCourseWare) · Exploring the Mysteries of System-Level Test (IEEE Asian Test Symposium)